US4743842A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tri-state circuit tester
Assignee: Grumman Corp
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Filing: 1987-03-11
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Granted: 1988-05-10
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Expires: 2007-03-11
Abstract
Abstract A testing circuit is capable of testing digital circuits, such as gates, in logic 1, logic 0 and Hi-Z conditions. To accomplish this end two comparators are connected to the output of the digital circuit undergoing test while second inputs of both comparators are respectively connected to different reference voltages. By comparing the voltage level at the output of the digital circuit undergoing test with programmable reference voltages, unique truth tables are established for an operative digital circuit undergoing test.
Inventors
- 👤 Joseph A. Langone
- 👤 Michael Ugenti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:39
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
154 words
A circuit for testing a tri-state digital device having a signal input for logic 1 and logic 0 levels, the device also having a tri-state enable input, the testing circuit comprising: first and second reference voltage points; voltage dividing means having a center contact connected to an output of the device and further having outer contacts connected to respective reference voltage points; first and second comparators each having a first input connected to a corresponding reference voltage point and a second input connected to the center point; and individual terminal means at the outputs of the comparators which carry logic 0 levels at both terminals when a logic 0 is present at the signal input, logic 1 levels at both terminals when a logic 1 is present at the signal input, logic 0 at one terminal and logic 1 at the other terminal when an enable signal is present at the tri-state enable input.
Claim 2
Dependent Claim
154 words
A circuit for testing a tri-state digital device having a signal input for logic 1 and logic 0 levels, the device also having a tri-state enable input, the testing circuit comprising: first and second reference voltage points; voltage dividing means having a center contact connected to an output of the device and further having outer contacts connected to respective reference voltage points; first and second comparators each having a first input connected to a corresponding reference voltage point and a second input connected to the center point; and individual terminal means at the outputs of the comparators which carry logic 0 levels at both terminals when a logic 0 is present at the signal input, logic 1 levels at both terminals when a logic 1 is present at the signal input, logic 0 at one terminal and logic 1 at the other terminal when an enable signal is present at the tri-state enable input.
Claim 3
Dependent Claim
18 words
The structure set forth in claim 1 wherein the voltage dividing means comprises a pair of matching resistors.
Claim 4
Dependent Claim
49 words
The structure set forth in claim 1 wherein the first reference voltage is maintained at an analog value less than the analog value of the logic 1 level; and the second reference voltage is maintained at an analog value greater than the analog value of a logic 0 level.
Claim 5
Dependent Claim
49 words
The structure set forth in claim 2 wherein the first reference voltage is maintained at an analog value less than the analog value of the logic 1 level; and the second reference voltage is maintained at an analog value greater than the analog value of a logic 0 level.
Claim 6
Independent Claim
330 words
A method for testing a tri-state digital device having a signal input for logic 1 and logic 0 levels, the device also having a tri-state enable input, the method comprising the following steps: making first and second reference voltages available at separate points; dividing the voltage between the points so that a center reference voltage point is obtained; connecting the output of a digital device to the center reference voltage point; at a first instant, making a first comparison between the first reference voltage and the voltage of a first logic level present at the center reference voltage point; at the first instant, making a second comparison between the second reference voltage and the voltage of a first logic level present at the center reference voltage point; determining whether the device operates satisfactorily with the first logic levels by comparing the first and second comparisons during the first instant wherein a match therebetween indicates satisfactory operation; at the second instant, making a first comparison between the first reference voltage and the voltage of a second logic level present at the center reference voltage point; at the second instant, making a second comparison between the second reference voltage and the voltage of a second logic level present at the center reference voltage point; determining whether the device operates satisfactorily with the second logic level by comparing the first and second comparisons during the second instant wherein a match therebetween indicates satisfactory operation; at a third instant, providing the device with a tri-state enable command and simultaneously making a first comparison between the first reference voltage and a reference voltage at the center reference voltage point; at the third instant, making a second comparison between the second reference voltage and the reference voltage present at the center reference voltage point; and determining during the third instant whether the device operates satisfactorily in a tri-state mode by comparing the first and second comparisons whereby a mismatch of these comparisons indicates satisfactory tri-state operation.
Claim 7
Independent Claim
330 words
A method for testing a tri-state digital device having a signal input for logic 1 and logic 0 levels, the device also having a tri-state enable input, the method comprising the following steps: making first and second reference voltages available at separate points; dividing the voltage between the points so that a center reference voltage point is obtained; connecting the output of a digital device to the center reference voltage point; at a first instant, making a first comparison between the first reference voltage and the voltage of a first logic level present at the center reference voltage point; at the first instant, making a second comparison between the second reference voltage and the voltage of a first logic level present at the center reference voltage point; determining whether the device operates satisfactorily with the first logic levels by comparing the first and second comparisons during the first instant wherein a match therebetween indicates satisfactory operation; at the second instant, making a first comparison between the first reference voltage and the voltage of a second logic level present at the center reference voltage point; at the second instant, making a second comparison between the second reference voltage and the voltage of a second logic level present at the center reference voltage point; determining whether the device operates satisfactorily with the second logic level by comparing the first and second comparisons during the second instant wherein a match therebetween indicates satisfactory operation; at a third instant, providing the device with a tri-state enable command and simultaneously making a first comparison between the first reference voltage and a reference voltage at the center reference voltage point; at the third instant, making a second comparison between the second reference voltage and the reference voltage present at the center reference voltage point; and determining during the third instant whether the device operates satisfactorily in a tri-state mode by comparing the first and second comparisons whereby a mismatch of these comparisons indicates satisfactory tri-state operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |