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US3601631A
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US
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Binary input controlled gate circuit for analog type signals
Assignee: HP Inc
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Filing: 1968-08-12
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Granted: 1971-08-24
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Expires: 1988-08-12
Abstract
Abstract A gate circuit includes a transistor which receives dual polarity analog-type input signals and conducts either as a forward or inverted gain amplifier or as two diodes to provide dual polarity output signals. The transistor is controlled at the base electrode thereof by resistor-diode logic circuitry responsive to binary signals having magnitudes greater than the duel polarity input signals. A plurality of the transistor gate circuits in combination permit time multiplexing of duel polarity signals to an analog type of load such as a magnetic head in an NRZ recording system.
Inventors
- 👤 Donald K Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:48
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
279 words
A binary input controlled signal gate comprising: a transistor having first and second main current carrying electrodes and a control electrode, said control electrode being either an N or a P type conductivity material; a signal source connected to said first main current carrying electrode, said signal source providing an analog signal within predetermined positive and negative voltage values; load terminal means connected to said second main current carrying electrode; control means including: a resistor connected to said control electrode; at least one diode connected to said control electrode, said diode having N and P type conductivity electrodes, the connected diode electrode and control electrode being of like conductivity type; a first voltage source providing a first binary output voltage level more positive than the predetermined positive voltage value of said signal source; a second voltage source providing a second binary output voltage level more negative than the predetermined negative voltage value of said signal source; means for selectively applying said first and second binary voltage levels to said resistor and said diode; said applying means being operable in a first mode to couple said first voltage source to at least one of said resistor and diode to condition said transistor to conduct zero current flow through said second main current carrying electrode coupled to said load terminal; and said applying means being operable in a second mode to couple said second voltage source to said resistor and each diode coupled to said control electrode to condition said transistor to conduct both forward and reverse current flow through said second main current carrying electrode; thereby to permit said transistor to provide an analog signal output having a dual polarity.
Claim 2
Dependent Claim
279 words
A binary input controlled signal gate comprising: a transistor having first and second main current carrying electrodes and a control electrode, said control electrode being either an N or a P type conductivity material; a signal source connected to said first main current carrying electrode, said signal source providing an analog signal within predetermined positive and negative voltage values; load terminal means connected to said second main current carrying electrode; control means including: a resistor connected to said control electrode; at least one diode connected to said control electrode, said diode having N and P type conductivity electrodes, the connected diode electrode and control electrode being of like conductivity type; a first voltage source providing a first binary output voltage level more positive than the predetermined positive voltage value of said signal source; a second voltage source providing a second binary output voltage level more negative than the predetermined negative voltage value of said signal source; means for selectively applying said first and second binary voltage levels to said resistor and said diode; said applying means being operable in a first mode to couple said first voltage source to at least one of said resistor and diode to condition said transistor to conduct zero current flow through said second main current carrying electrode coupled to said load terminal; and said applying means being operable in a second mode to couple said second voltage source to said resistor and each diode coupled to said control electrode to condition said transistor to conduct both forward and reverse current flow through said second main current carrying electrode; thereby to permit said transistor to provide an analog signal output having a dual polarity.
Claim 3
Dependent Claim
190 words
A circuit for time multiplexing a plurality of input signals into a single output providing positive, negative and zero signals, said multiplexing circuit comprising: a plurality of transistors, each having first and second main current carrying electrodes and a control electrode; a plurality of input signal sources connected respectively to the first main current carrying electrode of each of said plurality of transistors, said signal sources each providing a signal within predetermined positive and negative voltage values; means connecting said second main current carrying electrodes to a common output; a resistor connected to the control electrode of each of said transistors; at least one diode connected to the control electrode of each of said transistors; control means for sequentially conditioning said plurality of transistors to provide forward, reverse or zero collector current flow to said common output, said control means including: means providing binary voltage levels respectively greater than and less than the predetermined positive and Negative voltage values of said plurality of signal sources; and switching means for selectively applying said binary voltage levels to each of the resistors and diodes connected to the control electrodes of said transistors.
Claim 4
Dependent Claim
190 words
A circuit for time multiplexing a plurality of input signals into a single output providing positive, negative and zero signals, said multiplexing circuit comprising: a plurality of transistors, each having first and second main current carrying electrodes and a control electrode; a plurality of input signal sources connected respectively to the first main current carrying electrode of each of said plurality of transistors, said signal sources each providing a signal within predetermined positive and negative voltage values; means connecting said second main current carrying electrodes to a common output; a resistor connected to the control electrode of each of said transistors; at least one diode connected to the control electrode of each of said transistors; control means for sequentially conditioning said plurality of transistors to provide forward, reverse or zero collector current flow to said common output, said control means including: means providing binary voltage levels respectively greater than and less than the predetermined positive and Negative voltage values of said plurality of signal sources; and switching means for selectively applying said binary voltage levels to each of the resistors and diodes connected to the control electrodes of said transistors.
Claim 5
Dependent Claim
73 words
The circuit of claim 2, further including a bistable multivibrator having output means connectable to an analog type of load, and input means responsive to said forward and reverse collector current flow at said common output for respectively selecting negative and positive output voltage states of said multivibrator, said bistable multivibrator being operable to hold in memory a previously selected output state in response to said zero current flow at said common output.
Claim 6
Dependent Claim
148 words
The circuit of claim 3, said bistable multivibrator including: first and second transistors, each having emitter, collector and base electrodes; means connecting the emitter electrodes of said first and second transistors in parallel to a voltage source of one polarity; resistor means respectively connecting the collector electrodes of said first and second transistors to a voltage source having a polarity opposite to said one polarity voltage source; a resistor connecting the base of said first transistor to the collector of said second transistor; a resistor and a diode connected in series between the base electrode of said second transistor and the collector electrode of said first transistor; said input means of said multivibrator including means connecting the common output of said multiplexing circuit to the common junction of said series connected resistor and diode; and said output means being connected to the collector electrode of said second transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-23 | 1975-02-22 | 1975-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-23 | 1979-02-22 | 1979-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-23 | 1983-02-22 | 1983-08-24 | $7700.00 | Window Closed / Lapsed |