Clock recovery circuit and method

Claim 1

A method of recovering a data clock from an NRZI coded data bit stream using a source clock having a pulse generation rate which is an integer multiple, N, of the data bit time, said method comprising the steps of: (a) monitoring for a data state transition in the coded data stream; (b) if a data state transition is not detected, incrementing a counter; (c) if a data state transition is detected, resetting the counter; (d) generating a data clock pulse if the counter has reached the appropriate count, said data clock pulse being generated N/2 clock pulses after a data transition is detected and every N source clock pulses thereafter, until the counter is reset by another data state transition; and (e) repeating steps (a)-(d) at each pulse of the source clock.

Claim 2

A method of recovering a data clock from an NRZI coded data bit stream using a source clock having a pulse generation rate which is an integer multiple, N, of the data bit time, said method comprising the steps of: (a) monitoring for a data state transition in the coded data stream; (b) if a data state transition is not detected, incrementing a counter; (c) if a data state transition is detected, resetting the counter; (d) generating a data clock pulse if the counter has reached the appropriate count, said data clock pulse being generated N/2 clock pulses after a data transition is detected and every N source clock pulses thereafter, until the counter is reset by another data state transition; and (e) repeating steps (a)-(d) at each pulse of the source clock.