Coarse initial timing recovery circuit

Claim 2

In combination wIth a digital data receiver of the multidata level type that provides a baseband signal containing intersymbol interference components along with transmitted digital data, transmitted at a baud rate, the improvement of an initial timing recovery circuit comprising in combination: clock means for providing a train of pulses having a repetition rate greater than the baud rate of the transmitted signal; a pulse ADD/DELETE means for receiving said provided pulse train and for adding or deleting pulses from said pulse train in response to ADD or DELETE signals, respectively, in order to change the phase of said pulse train; frequency divider means for dividing the frequency of the pulse train from said ADD/DELETE means down to the baud signaling frequency; threshold crossing detector means receiving as inputs the received baseband signal and at least one threshold level signal of an absolute amplititude approximately equal to the amplitude of the main peak of the waveform received in response to a single transmitted pulse of unity amplitude, said detector means providing an output signal indicative of said baseband signal amplitude crossing said threshold amplitude level; and EARLY/LATE detector means for sensing the output pulse train from said frequency divider means and for comparing the occurrence of each pulse in said pulse train against the output signal from said threshold crossing detector means, and providing an ADD signal to said ADD/DELETE means when the compared pulse occurs prior to the occurrence of the output signal and a DELETE signal when the compared pulse occurs after the start of the output signal, said EARLY/LATE detector means thereby averaging the response to the amplitude threshold crossings of said baseband signal and establishing a timing reference in accordance with the average of the said amplitude threshold crossings.

Claim 3

The combination according to claim 1 wherein there are provided two said threshold levels of equal absolute amplitude but of opposite polarity.

Claim 4

The combination according to claim 2 wherein said EARLY/LATE detector means is comprised of: first and second AND gates, each receiving as an input the output signal from said threshold crossing detector means; a one-shot multivibrator receiving as an input the signal from said frequency divider means, said multivibrator changing state upon receipt of said frequency divider signal, the output of said multivibrator being fed to said first AND gate as an input signal so as to gate the signal from said threshold crossing detector means to said ADD/DELETE circuit as said ADD signal. a NOT circuit receiving the signal from said one-shot multivibrator and providing an output signal to said second AND gate when none exists at the output of said mlutivibrator, such that the signal from said threshold crossing detector means is gated to said ADD/DELETE circuit as said DELETE signal.

Claim 5

The combination according to claim 2 wherein said threshold crossing detector comprises: a first comparator means for receiving said baseband signal and one of said threshold level signals and providing an output signal when said baseband signal amplitude crosses said one threshold level; a second comparator means for receiving said baseband signal and the other of said threshold level signals and providing an output signal when said baseband amplitude crosses said other threshold level; and OR gate means receiving the output signals from said first and said second comparator means and providing an output signal indicative of the presence of an output signal from said first or second comparator.

Claim 6

The combination according to claim 4 and further comprising: means for receiving the output signal from said OR gate means and for transforming said output signal into a pulse output signal corresponding in frequency and phase to said output signal.

Claim 7

The combination according to claim 4 and further comprising: Differentiator means for receiving and differentiating the output signal from said OR gate means; and rectifier means for rectifying said differential signals, said rectified signals fed to the input of said EARLY/LATE detector means.

Claim 8

In combination with a digital data receiver of the multidata level type that provides a baseband signal containing intersymbol interference components along with transmitted digital data, transmitted at a baud rate, the improvement of an initial timing recovery circuit comprising in combination: clock means for providing a train of pulses having a repetition rate greater than the baud rate of the transmitted signal; a pulse ADD/DELETE means for receiving said provided pulse train and for adding or deleting pulses from said pulse train in response to ADD or DELETE signals, respectively, in order to change the phase of said pulse train; frequency divider means for dividing the frequency of the pulse train from said ADD/DELETE means down to the baud signaling frequency; threshold crossing detector means for receiving as an input the received baseband signal and for providing an output signal indicative of whether said baseband signal has an amplitude above or below a threshold set halfway between data levels; said detector means comprising: the compared after the the compared of the output a first comparator means for receiving said baseband signal and a first threshold level signal set midway between data levels and for providing an output signal when said baseband signal has an amplitude greater than said first threshold level; a second comparator means for receiving said baseband signal and a second threshold level signal set midway between data levels and for providing an output signal when said baseband signal has an amplitude less than said second threshold level; OR gate means receiving the output signals from said first and said second comaprator means and for providing an output signal indicative of the presence of an output signal from said first or said second comparator; and EARLY/LATE detector means for sensing the output pulse train from said frequency divider means and for comparing the occurrence of each pulse in said pulse train against the output signal from said threshold crossing detector means, and providing an ADD signal to said ADD/DELETE means when the composed pulse occurs prior to the occurrence of the output signal and a DELETE signal when the compound pulse occurs after the start of the output signal.

Claim 9

In combination with a digital data receiver of the multidata level type that provides a baseband signal containing intersymbol interference components along with transmitted digital data, transmitted at a baud rate, the improvement of an initial timing recovery circuit comprising in combination: clock means for providing a train of pulses having a repetition rate greater than the baud rate of the transmitted signal; a pulse ADD/DELETE means for receiving said provided pulse train and for adding or deleting pulses from said pulse train in response to ADD or DELETE signals, respectively, in order to change the phase of said pulse train; frequency divider means for dividing the frequency of the pulse train from said ADD/DELETE means down to the baud signaling frequency; threshold crossing detector means for receiving as an input the received baseband signal and for providing an output signal indicative of whether said baseband signal has an amplitude above or below a threshold set halfway between data levels; said detector means comprising: the compared after the the compared of the output a first comparator means for receiving said baseband signal and a first threshold level signal set midway between data levels and for providing an output signal when said baseband signal has an amplitude greater than said first threshold level; a second comparator means for receiving said baseband signal and a second threshold level signal set midway between data levels and for providing an output signal when said baseband signal has an amplitude less than said second threshold level; OR gate means receiving the output signals from said first and said second comaprator means and for providing an output signal indicative of the presence of an output signal from said first or said second comparator; and EARLY/LATE detector means for sensing the output pulse train from said frequency divider means and for comparing the occurrence of each pulse in said pulse train against the output signal from said threshold crossing detector means, and providing an ADD signal to said ADD/DELETE means when the composed pulse occurs prior to the occurrence of the output signal and a DELETE signal when the compound pulse occurs after the start of the output signal.

Claim 10

The combination according to claim 7 and further comprising: means for receiving the output signal from said OR gate means and for transforming said output signal into a pulse output signal corresponding in frequency and phase to said output signal.

Claim 11

The combination according to claim 7 and further comprising: differentiator means for receiving and differentiating the output signal from said OR gate means; rectifier means for rectifying said differentiated signals, said rectified signals fed to the input of said EARLY/LATE detector means.

Claim 12

In combination with a pulsed data receiver of the multidata level type that has an impulse response such that a transmitted pulse generates a received waveform having the shape of a main peak and trailing peaks of lesser amplitudes with said pulses transmitted at a baud rate to form a received signal containing intersymbol interference components, the improvement of an initial timing recovery circuit comprising in combination: means providing a pulse train having a repetition rate greater than the baud rate of transmitted pulses; a pulse ADD/DELETE means for receiving said provided pulse train and for adding or deleting pulses from said pulse train in response to ADD or DELETE signals, respectively, in order to change the phase of said pulse train; frequency divider means for dividing the frequency of the pulse train from said ADD/DELETE means down to the Baud signaling frequency: threshold crossing detector mean having as an input said received signal and at least one threshold level signal of an absolute amplitude approximately equal to the amplitude of the main peak of the waveform received in response to a single transmitted pulse of unity amplitude, said detector means providing an output pulse each time said received signal amplitude crosses said threshold amplitude level; EARLY/LATE detector means for sensing the output pulse train from said frequency divider means and for comparing the occurrence of each pulse in said pulse train against the output from said threshold crossing detector means, and providing an ADD signal to said ADD/DELETE means when the compared pulse occurs prior to the occurrence of the output pulse and a DELETE signal when the compared pulse occurs after the start of the output pulse. said EARLY/LATE detector means thereby averaging the response to the amplitude threshold crossings of said baseband signal and establishing a timing reference in accordance with the average of the said amplitude threshold crossings.

Claim 13

In combination with a pulsed data receiver of the multidata level type that has an impulse response such that a transmitted pulse generates a received waveform having the shape of a main peak and trailing peaks of lesser amplitudes with said pulses transmitted at a baud rate to form a received signal containing intersymbol interference components, the improvement of an initial timing recovery circuit comprising in combination: means providing a pulse train having a repetition rate greater than the baud rate of transmitted pulses; a pulse ADD/DELETE means for receiving said provided pulse train and for adding or deleting pulses from said pulse train in response to ADD or DELETE signals, respectively, in order to change the phase of said pulse train; frequency divider means for dividing the frequency of the pulse train from said ADD/DELETE means down to the Baud signaling frequency: threshold crossing detector mean having as an input said received signal and at least one threshold level signal of an absolute amplitude approximately equal to the amplitude of the main peak of the waveform received in response to a single transmitted pulse of unity amplitude, said detector means providing an output pulse each time said received signal amplitude crosses said threshold amplitude level; EARLY/LATE detector means for sensing the output pulse train from said frequency divider means and for comparing the occurrence of each pulse in said pulse train against the output from said threshold crossing detector means, and providing an ADD signal to said ADD/DELETE means when the compared pulse occurs prior to the occurrence of the output pulse and a DELETE signal when the compared pulse occurs after the start of the output pulse. said EARLY/LATE detector means thereby averaging the response to the amplitude threshold crossings of said baseband signal and establishing a timing reference in accordance with the average of the said amplitude threshold crossings.

Claim 14

The combination according to claim 10 wherein said EARLY/LATE detector means is comprised of: first and second AND gates, each receiving as an input the output signal from said threshold crossing detector means; a one-shot multivibrator receiving as an input the signal from said frequency divider means, said multivibrator changing state upon receipt of said frequency divider signal, the output of said multivibrator being fed to said first AND gate as an input signal so as to gate the signal from said threshold crossing detector means to said ADD/DELETE circuit as said ADD signal; a NOT circuit receiving the signal from said one-shot multivibrator and providing an output signal to said second AND gate when none exists at the output of said multivibrator, such that the signal from said threshold crossing detector mkans is gated to said ADD/DELETE circuit as said DELETE signal.