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US4740891A
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Asynchronous state machine
Assignee: Tektronix Inc
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Filing: 1985-05-06
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Granted: 1988-04-26
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Expires: 2005-05-06
Abstract
Abstract An asychronous state machine waits a variable length of time after first detecting a change in input state before initiating a machine state change, the new machine state being a function of the previous machine state and the input state at the end of the waiting time, thereby allowing multiple, non-simultaneous input changes to occur during said waiting time without initiating intermediate state changes. The waiting time is a function of the current state of the machine. One state variable of a set characterizing the current state of the machine indicates whether the current state is an interim state in a sequence of states occurring after an input state change. Following a machine state change, this sequencing state variable initiates a subsequent state change, in the absence of any further input state changes, when the sequencing state variable associated with the current machine state indicates that the current machine state is such an interim state of a sequence of states.
Inventors
- 👤 Donald C. Kirkpatrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 23:41
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
109 words
A state machine comprising: means for storing a current data set including a current machine state, a current output state, and a current timing state; means for generating a next data set, the next data set being a function of the current machine state and of a current input state; and means for monitoring the current input state and for producing a state change signal a variable time following a change in the current input state, said state change signal causing the storing means to store the next data set in place of the current data set, whereby said variable time is a function of the current timing state.
Claim 2
Dependent Claim
109 words
A state machine comprising: means for storing a current data set including a current machine state, a current output state, and a current timing state; means for generating a next data set, the next data set being a function of the current machine state and of a current input state; and means for monitoring the current input state and for producing a state change signal a variable time following a change in the current input state, said state change signal causing the storing means to store the next data set in place of the current data set, whereby said variable time is a function of the current timing state.
Claim 3
Dependent Claim
46 words
A state machine as recited in claim 1 wherein the generating means comprises an addressable memory device, the memory device being addressed by the current machine state and the current input state, and the next data set being stored at the location in memory so addressed.
Claim 4
Dependent Claim
88 words
A state machine as recited in claim 1 wherein the monitoring means comprises: means for detecting a change in the current input state and for outputtting a difference signal in response thereto and for stopping outputting the difference signal when the state change signal terminates; and means for initiating the state change signal the selected time after receiving the difference signal from the detecting means and for terminating the state change signal when the difference signal terminates, the initiating means having the current timing state as an input.
Claim 5
Dependent Claim
127 words
A state machine as recited in claim 3 wherein the detecting means comprises: a plurality of transparent latches having inputs and outputs to receive the current input state at the inputs and output a latched or current version of the inupt data at the outputs, with the oututs being latched during periods when the state change signal is inactive and the outputs tracking the inputs when the state change signal is active; and a plurality of exclusive OR gates to compare the inputs of the transparent latches with the outputs of the transparent latches; and an output gate to output the difference signal in response to differences between the inputs and the output of the transparent latches when such differences are detected by the exclusive OR gates.
Claim 6
Dependent Claim
106 words
A state machine as recited in claim 3 wherein the initiating means comprises: an oscillator; a shift register, the shift register being reset by the difference signal, and the shift register shifting a constantly asserted input signal in response to signals from the oscillator; and a multiplexer having the output of the shift register and the current timing state as inputs and producing the state change signal at an output when the input signal from the shift register reaches the value of the multiplexer input selected by the current timing state and terminating the state change signal when the differences signal on an enable input terminates.
Claim 7
Dependent Claim
145 words
A state machine comprising: means for storing a current data set including a current machine state, a current output state, a current timing state, and a sequence bit; means for generating a next data set, the next data set being a function of the current machine state and of a current input state; means for monitoring the current input state and a sequence signal and for producing a state change signal a variable time following a change in the current input state or sequence signal, said state change signal causing the storing means to store the next data set in place of the current data set, whereby said variable time is a function of the current timing state. means for determining the status of the sequence bit and for producing the sequence signal when the state change signal occurs and the sequence bit is set.
Claim 8
Dependent Claim
145 words
A state machine comprising: means for storing a current data set including a current machine state, a current output state, a current timing state, and a sequence bit; means for generating a next data set, the next data set being a function of the current machine state and of a current input state; means for monitoring the current input state and a sequence signal and for producing a state change signal a variable time following a change in the current input state or sequence signal, said state change signal causing the storing means to store the next data set in place of the current data set, whereby said variable time is a function of the current timing state. means for determining the status of the sequence bit and for producing the sequence signal when the state change signal occurs and the sequence bit is set.
Claim 9
Dependent Claim
46 words
A state machine as recited in claim 6 wherein the generating means comprises an addressable memory device, the memory device being addressed by the current machine state and the current input state, and the next data set being stored at the location in memory so addressed.
Claim 10
Dependent Claim
92 words
A state machine as recited in claim 6 wherein the monitoring means comprises: means for detecting a change in the current input state or the sequence signal and for outputtting a difference signal in response thereto and for stopping outputting the difference signal when the state change signal terminates; and means for initiating the state change signal the selected time after receiving the difference signal from the detecting means and for terminating the state change signal when the difference signal terminates, the initiating means having the current timing state as an input.
Claim 11
Dependent Claim
136 words
A state machine as recited in claim 8 wherein the detecting means comprises: a plurality of transparent latches having inputs and outputs to receive the current input state data and the sequence signal at the inputs and output a latched or current version of the input data and the sequence signal at the outputs, with the outputs being latched during periods when the state change signal is inactive and the outputs tracking the inputs when the state change signal is active; and a plurality of exclusive OR gates to compare the inputs of the transparent latches with the outputs of the transparent latches; and an output gate to output the difference signal in response to differences between the inputs and the outputs of the transparent latches when such differences are detected by the exclusive OR gates.
Claim 12
Dependent Claim
107 words
A state machine as recited in claim 8 wherein the initiating means comprises; an oscillator; a shift register, the shift register being reset by the the difference signal, and the shift register shifting a constantly asserted input signal in response to signals from the oscillator; and a multiplexer having the output of the shift register and the current timing state as inputs and producing the state change signal at an output when the input signal from the shift register reaches the value of the multiplexer input selected by the current timing state and terminating the state change signal when the difference signal on an enable input terminates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |