Heterojunction-gate field-effect transistor enabling easy control of threshold voltage

Claim 2

A heterojunction gate field effect transistor comprising: an active layer of a first semiconductor material; source and drain impurity doped regions formed in a surface portion of said active layer; an intermediate layer of a second semiconductor material formed on said active layer between said source and drain regions, said second semiconductor material having a wider energy band-gap than said first semiconductor material and inducing a two-dimensional charge layer in said surface portion of said active layer between said source and drain regions; and a gate electrode formed on said intermediate layer, said gate electrode including a mixed semiconductor crystal comprised of at least two III-V compound semiconductors, and being doped with impurities, and said gate electrode receiving an electric potential to control the conductivity of said two-dimensional charge layer.

Claim 3

A heterojunction gate field effect transistor as claimed in claim 1, wherein said mixed semiconductor crystal consists of two compound semiconductors.

Claim 4

A heterojunction gate field effect transistor as claimed in claim 1, wherein said mixed semiconductor crystal is a GaP-InAs mixed crystal.

Claim 5

A heterojunction gate field effect transistor as claimed in claim 2, wherein said active layer is formed on a substrate of insulating or semi-insulating material.

Claim 6

A heterojunction gate field effect transistor as claimed in claim 4, wherein said substrate is a semi-insulating GaAs substrate, said first and second semiconductor materials being an intrinsic or slightly P-type GaAs and Al 1-x Ga x As, respectively.

Claim 7

A heterojunction gate field effect transistor as claimed in claim 5, wherein said mixed semiconductor crystal is a GaP-InAs mixed crystal.

Claim 8

A heterojunction gate field effect transistor as claimed in claim 1, wherein said mixed semiconductor crystal consists of four III-V compound semiconductors.

Claim 9

A heterojunction gate field effect transistor as claimed in claim 7, wherein said active layer is formed on a substrate of a semi-insulating GaAs, said first and second semiconductor materials being a semi-insulating or slightly P-type GaAs and Al 1-x Ga x As, respectively.

Claim 10

A heterojunction gate field effect transistor as claimed in claim 8, wherein said mixed semiconductor crystal is selected from the group of mixed semiconductor crystals of AlSb-Gap-InAs-GaP and GaSb-GaP-InAs-GaP.

Claim 11

A heterojunction gate field effect transistor comprising: an active layer of a III-V compound semiconductor material; source and drain impurity doped regions formed in a surface portion of said active layer; an intermediate layer of a second semiconductor material formed on said active layer between said source and drain regions, said second semiconductor material having a wider energy band-gap than said first semiconductor material and inducing a two-dimensional charge layer in said surface portion of said active layer between said source and drain regions; and a gate electrode formed on said intermediate layer and made of a third semiconductor material, said third semiconductor material being an impurity doped region composed of a mixture of at least two mixed crystals selected from the group consisting of GaP, InAs, AlP, InP, GaAs, GaSb, AlSb and AlAs; and said gate electrode receiving an electrical potential to control the conductivity of said two-dimensional charge layer.

Claim 12

A heterojunction gate field effect transistor comprising: an active layer of a III-V compound semiconductor material; source and drain impurity doped regions formed in a surface portion of said active layer; an intermediate layer of a second semiconductor material formed on said active layer between said source and drain regions, said second semiconductor material having a wider energy band-gap than said first semiconductor material and inducing a two-dimensional charge layer in said surface portion of said active layer between said source and drain regions; and a gate electrode formed on said intermediate layer and made of a third semiconductor material, said third semiconductor material being an impurity doped region composed of a mixture of at least two mixed crystals selected from the group consisting of GaP, InAs, AlP, InP, GaAs, GaSb, AlSb and AlAs; and said gate electrode receiving an electrical potential to control the conductivity of said two-dimensional charge layer.

Claim 13

A heterojunction gate field effect transistor as claimed in claim 10, wherein said first semiconductor material is a semi-insulating or slightly P-type GaAs, said second semiconductor material being Al 1-x Ga x As.

Claim 14

A heterojunction gate field effect transistor as claimed in claim 11, wherein said active layer is formed on a substrate of insulator or semi-insulator material.

Claim 15

A heterojunction gate field effect transistor as claimed in claim 12, wherein said substrate is made of semi-insulating GaAs.

Claim 16

A heterojunction gate field effect transistor, comprising: an active layer of a first semiconductor material; source and drain impurity doped regions formed in a surface portion of said active layer; an intermediate layer of a second semiconductor material formed on said active layer between said source and drain regions, said second semiconductor material having a wider energy band-gap than said first semiconductor material and inducing a two-dimensional charge layer in said surface portion of said active layer between said source and drain regions; a gate electrode formed on said intermediate layer and made of a third semiconductor material comprised of at least two III-V compound semiconductors; and means for adjusting the threshold value of said heterojunction gate field effect transistor by controlling relative proportions of said at least two III-V compound semiconductors in said third semiconductor layer.

Claim 17

A heterojunction gate field effect transistor, comprising: an active layer of a first semiconductor material; source and drain impurity doped regions formed in a surface portion of said active layer; an intermediate layer of a second semiconductor material formed on said active layer between said source and drain regions, said second semiconductor material having a wider energy band-gap than said first semiconductor material and inducing a two-dimensional charge layer in said surface portion of said active layer between said source and drain regions; a gate electrode formed on said intermediate layer and made of a third semiconductor material comprised of at least two III-V compound semiconductors; and means for adjusting the threshold value of said heterojunction gate field effect transistor by controlling relative proportions of said at least two III-V compound semiconductors in said third semiconductor layer.