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US4737792A
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Counter-based simulated target generator
Assignee: Northrop Grumman Corp
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Filing: 1986-06-20
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Granted: 1988-04-12
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Expires: 2006-06-20
Abstract
Abstract Apparatus and a method for generating simulated target signals for testing a radar system is disclosed. The fundamental timing intervals for each pulse of the simulated target signal are generated based upon the contents of a high-speed continuously running digital counter. The resolution of the system is determined by the clock rate utilized to increment the counter. Simulated target signals are generated by utilizing an adder to add the desired range to the contents of the counter at a time interval corresponding to each pulse of the radar sync signal. The output signal of the adder corresponds to the expected output of the counter at a time corresponding to the return pulse associated with the transmit sync signal. These values are stored in a digital memory at sequential address locations. The stored values are sequentially read to produce at the output of the memory a digital signal corresponding to the value of the high-speed counter at the time that the return pulse is to be generated. The output data of the memory is compared to the contents of the counter and when they are found to be equal, a pulse of the simulated target signal is generated and the read address to the memory is incremented one count. This process is repeated for each pulse of the transmit sync signal to generate at the output a pulse train with each pulse of the output being delayed from its corresponding pulse of the transmit sync signal by the value determined by the range signal.
Inventors
- 👤 Donald J. Grone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:33
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/40; G01S7/4052; G01S7/4082; G09; G09B; G09B9/00; G09B9/54
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
184 words
A target generator for generating test signals for a radar system comprising: (a) a counter circuit having a digital output signal which is continuously incremented by a pulsed clock signal, without being reset; (b) an adder circuit receiving as inputs the digital output signal of said counter circuit and a predetermined digital number specifying the range to the simulated target, said adder circuit producing a digital output number in response to an externally generated transmit sync pulse, said digital output number being equal to the sum of the value of said digital output signal when said sync pulse occurs, and the predetermined digital number; (c) a random access memory for selectively storing the digital output number of said adder, wherein said adder digital output number corresponds to an expected value of said counter digital output signal when a simulated target return is to be generated; and (d) means for reading said adder digital output number from said memory and for comparing said adder digital output number with said digital output signal of said counter to generate a simulated target return when they are equal.
Claim 2
Dependent Claim
184 words
A target generator for generating test signals for a radar system comprising: (a) a counter circuit having a digital output signal which is continuously incremented by a pulsed clock signal, without being reset; (b) an adder circuit receiving as inputs the digital output signal of said counter circuit and a predetermined digital number specifying the range to the simulated target, said adder circuit producing a digital output number in response to an externally generated transmit sync pulse, said digital output number being equal to the sum of the value of said digital output signal when said sync pulse occurs, and the predetermined digital number; (c) a random access memory for selectively storing the digital output number of said adder, wherein said adder digital output number corresponds to an expected value of said counter digital output signal when a simulated target return is to be generated; and (d) means for reading said adder digital output number from said memory and for comparing said adder digital output number with said digital output signal of said counter to generate a simulated target return when they are equal.
Claim 3
Dependent Claim
169 words
A target generator for generating range test signals for testing a radar system, comprising in combination: (a) means for generating a digital number which is continuously incremented at a selected rate, without being reset; (b) means for combining the value of said digital number existing upon the occurrence of an externally generated transmit sync pulse, with a digital range signal to generate a digital comparison signal, said digital comparison signal being equal to the sum of the value of said digital number when said sync pulse occurs and a predetermined number representative of the range to a simulated target, and corresponding to an expected value of said digital number when a simulated target signal is to be generated; (c) memory means for storing at least one value of said digital comparison signal; (d) memory read control means for reading said digital comparison signal; and (e) compare means for comparing said digital comparison signal to said digital number and for generating a simulated target return signal when they are equal.
Claim 4
Dependent Claim
169 words
A target generator for generating range test signals for testing a radar system, comprising in combination: (a) means for generating a digital number which is continuously incremented at a selected rate, without being reset; (b) means for combining the value of said digital number existing upon the occurrence of an externally generated transmit sync pulse, with a digital range signal to generate a digital comparison signal, said digital comparison signal being equal to the sum of the value of said digital number when said sync pulse occurs and a predetermined number representative of the range to a simulated target, and corresponding to an expected value of said digital number when a simulated target signal is to be generated; (c) memory means for storing at least one value of said digital comparison signal; (d) memory read control means for reading said digital comparison signal; and (e) compare means for comparing said digital comparison signal to said digital number and for generating a simulated target return signal when they are equal.
Claim 5
Independent Claim
122 words
A method of generating range test signals for testing a radar system, comprising the steps of: generating a digital number which is continuously incremented at a selected rate, without being reset; receiving an externally generated transmit sync pulse; combining the value of said digital number when said sync pulse occurs with a digital range signal to generate a digital comparison signal, said digital comparison signal corresponding to the expected value of said digital number when a simulated target signal is to be generated; storing at least one value of said digital comparison signal; comparing the stored digital comparison signal with said digital number; and generating a simulated target return signal when the stored digital comparison signal and the digital number are equal.
Claim 6
Independent Claim
122 words
A method of generating range test signals for testing a radar system, comprising the steps of: generating a digital number which is continuously incremented at a selected rate, without being reset; receiving an externally generated transmit sync pulse; combining the value of said digital number when said sync pulse occurs with a digital range signal to generate a digital comparison signal, said digital comparison signal corresponding to the expected value of said digital number when a simulated target signal is to be generated; storing at least one value of said digital comparison signal; comparing the stored digital comparison signal with said digital number; and generating a simulated target return signal when the stored digital comparison signal and the digital number are equal.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-12 | 1991-10-12 | 1992-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-12 | 1995-10-12 | 1996-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-12 | 1999-10-12 | 2000-04-12 | $7700.00 | Window Closed / Lapsed |