Method of and device for the digital cancellation of the echo generated in connections with time-varying characteristics

Claim 1

An adaptive digital echo canceler for an echo-channel pulse response, said pulse response comprises a first interval, a second interval and a third interval, and wherein: the first interval consists of flat-delay; the second interval has a time period less than voice time periods; the third interval has a time period greater than voice time periods, and said canceler comprises: a processor unit comprising a control unit (MUX1, SEQ, ROMP, PIPE), a computing unit (MAC), first, second, and third random access data memories (RAM1, RAM2, RAMA), a read only memory (ROMC) containing determined constant values, said memories being addressed by first, second, and third programmable up/down counters (CT1, CT2, CT3) connected to an address bus (ADRB), data input/output devices (RU, MUX2) connected to an internal bus (BUSP), said first data memory (RAM1) storing coefficients h(m) where m(0<m<M) is the index of an m-th filter tap of a transversal filter, said coefficients h(m) being present on said internal bus (BUSP), said first data memory (RAM1) supplying the coefficients h(m) onto a first input bus (BF1) of said computing unit (MAC), said second data memory (RAM2) implements a delay line of said transversal filter storing the last M samples x(k), present on said input bus (BF2) of said computing unit (MAC), k being a time variable in discrete form, said third data memory (RAMA) storing bit configurations present on said address bus (ADRB), the output of said computing unit being connected to said internal bus (BUSP) which can be connected to said address bus by a bidirectional receiver (PA1), for determining said second interval, said first memory stores said coefficients h(m), said indexes of said coefficients h(m) and a maximum absolute value of said coefficients being iteratively calculated, said maximum value being stored in a first register (RD) connected to said first internal bus (BF1), and said computing unit (MAC) computing for each of said coefficients a first difference between an absolute value of each of said coefficients and said maximum value, wherein if said first difference is positive, said computing unit writes in said first memory (RAM1), through a second register (PF1), which connects said internal bus with said first internal bus (BF1), the absolute value of each of said coefficients in the position of said maximum absolute value, and in said third data memory a second difference between the addresses of the first of said coefficients of said second interval and of one of said coefficients, said second difference being a counting value attained by said second programmable counter (CT2) being incremented, each of said coefficients being examined and a third difference being derived between the address of the first of said coefficients and the address of a maximum value of said coefficients of said second interval, and when all the coefficients of said second interval have been examined, said computing unit adds in a first addition the address of said first of said coefficients and the value of said second difference forming a first result, being written in said third memory (RAMA) and transferred onto said first internal bus (BF1) and a second internal bus (BF2) through a second register (RF1) and a third register (RF2) connected to said internal bus (BUSP) and said first result being written into said third memory (RAMA) as an address of said first of said coefficients of a new second interval, said computing unit then carrying out a second addition between the address of sample X(k-W), the beginning of said second interval having an index W corresponding to a coefficient h(W) stored in said third data memory (RAMA) and transferred through said third register (RF2) on said second internal bus (BF2) and said second difference, forming a second result, and writing said second result in said third memory (RAMA), in an address of the first result, as a new address of sample x(k-W), and if the first result is negative, or greater than W-N, N being the effective tap number of said transversal filter, an address for coefficients h(0) is written in said third memory as an address of the first of said coefficients of the new second interval, and an address of sample x(k) being a new address of sample x(k-W).