Echo canceller using end delay measurement

Claim 2

In a communication system having first and second one way transmission paths, an echo canceller which comprises: an end delay analyzer circuit having first and second inputs electrically connected to the first and second paths, respectively, and providing a control signal at an output, which signal is a measure of an end delay; a variable delay circuit having one input electrically connected to said first path, having a second input receiving said control signal and being responsive thereto to adjust said variable delay so as to provide at an output thereof a delayed sample of a first path signal with a delay that is equal to said end delay; transversal filter echo synthesizer means responsive to said delayed sample of the signal on said first path and producing an output signal; and means connected in said second path for algebraically combining signals in said second path with the output signal from said echo synthesizer means; said synthesizer means being responsive to an algebraically combined signal at an output of said combining means for providing an echo replica signal as the output signal of said synthesizer means; said end delay analyzer further comprising: first means for limiting current and delayed signal samples from said first path; second means for limiting a signal from said second path; and sequential comparator means for comparing the limited signals from said first and second limiting means to determine the delay location at which a maximum correlation, i.e., a match, is obtained.

Claim 3

An echo canceller as in claim 1 wherein said delay analyzer operates in accordance with the following algorithm W.sub.m.sup.i =W.sub.m.sup.i-1 (1-1/L.sub.1)+sign(X.sup.i-m)sign(Y.sup.i /L.sub.2), where W represents a weight, m is an index, i is a sample index, L 1 and L 2 are constants, X i is an input signal sample, and Y i is a return signal sample, to measure the correlation between the first and second paths recursively, in order to determine a "match", and provide a delay index therefor.

Claim 4

An echo canceller as in claim 2 wherein said variable delay circuit comprises: a clock; a counter responsive to said clock for providing a count interval; a subtractor responsive to both the count interval and said delay index for providing a read output; a selector responsive to said clock pulse for coupling said read output from the subtractor as an address signal; and means for storing the sampled inputs from said first path and responsive to the address signal for providing as delayed outputs signal samples in said storing means in accordance with said end delay as characterized by said delay index.

Claim 5

An echo canceller as in claim 3 wherein said selector is a 2 to 1 selector.

Claim 6

An echo canceller as in claim 4 wherein said means for storing is a random access memory (RAM).

Claim 7

In a communication system having first and second one way transmission paths, an echo canceller which comprises: an end delay analyzer circuit having first and second inputs electrically connected to the first and second paths, respectively, and providing a control signal at an output, which signal is a measure of an end delay; a variable delay circuit having one input electrically connected to said first path, having a second input receiving said control signal and being responsive thereto to adjust said variable delay, so as to provide at an output a delayed sample of a first path signal with a delay that is equal to said end delay; transversal filter echo synthesizer means responsive to said delayed sample of the signal on said first path and producing an output signal; and means connected in said second path for algebraically combining signals in said second path with the output signal from said echo synthesizer means; said synthesizer means being responsive to an algebraically combined signal at an output from said combining means for providing an echo replica signal as the output signal of said synthesizer means; said end delay analyzer further comprising: means for sequentially delaying samples of the first path signal; means for multiplying said delayed signal samples with a current signal sample from said second path; and means for comparing said multiplied signal samples to determine the delay location at which there is a maximum correlation, i.e., a match, and provide a delay index thereof; said variable delay circuit further comprising: a clock; a counter responsive to said clock for providing a count interval; a subtractor responsive to both the count interval and said delay index for providing a read output; a selector responsive to said clock pulse for coupling said read output from the subtractor as an address signal; and means for storing sample inputs from said first path and responsive to the address signal for providing as delayed outputs signal samples in said storing means in accordance with said end delay as characterized by said delay index.

Claim 8

In a communication system having first and second one way transmission paths, an echo canceller which comprises: an end delay analyzer circuit having first and second inputs electrically connected to the first and second paths, respectively, and providing a control signal at an output, which signal is a measure of an end delay; a variable delay circuit having one input electrically connected to said first path, having a second input receiving said control signal and being responsive thereto to adjust said variable delay, so as to provide at an output a delayed sample of a first path signal with a delay that is equal to said end delay; transversal filter echo synthesizer means responsive to said delayed sample of the signal on said first path and producing an output signal; and means connected in said second path for algebraically combining signals in said second path with the output signal from said echo synthesizer means; said synthesizer means being responsive to an algebraically combined signal at an output from said combining means for providing an echo replica signal as the output signal of said synthesizer means; said end delay analyzer further comprising: means for sequentially delaying samples of the first path signal; means for multiplying said delayed signal samples with a current signal sample from said second path; and means for comparing said multiplied signal samples to determine the delay location at which there is a maximum correlation, i.e., a match, and provide a delay index thereof; said variable delay circuit further comprising: a clock; a counter responsive to said clock for providing a count interval; a subtractor responsive to both the count interval and said delay index for providing a read output; a selector responsive to said clock pulse for coupling said read output from the subtractor as an address signal; and means for storing sample inputs from said first path and responsive to the address signal for providing as delayed outputs signal samples in said storing means in accordance with said end delay as characterized by said delay index.

Claim 9

An echo canceller as in claim 6 wherein said selector is a two to one selector.

Claim 10

An echo canceller as in claim 7 wherein said means for storing is a random access memory (RAM).