Logic circuit having a test data loading function

Claim 2

A logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising: a first-stage logic circut having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a clock signal input terminal for receiving a clock signal, a noninverted signal output terminal, and an inverted signal output terminal; means for providing an enable signal, first and second data signals and a test data signal such that said enable signal has a first constant value when said first input data or said second input data is received and said enable signal has a second constant value when said test data is received, said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal.

Claim 3

A logic circuit as set forth in claim 1, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal.

Claim 4

A logic circuit as set forth in claim 2, wherein said first-stage logic circuit comprises: a first AND gate having four inputs respectively connected to said noninverted signal output terminal, to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit; a second gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit; a third gate having three inputs respectively connected to said test data terminal, to said enable terminal through an inverter, and to said one of the outputs of said pre-stage logic circuit; and a forth gate having three inputs respectively connected to the outputs of said first, second and third gates and having an output connected to said input of said second-stage logic circuit.

Claim 5

A logic circuit as set forth in claim 2, wherein said final-stage logic circuit comprises cross-coupled first and second gates, and said pre-stage logic circuit comprises a third gate having two inputs and an output, a fourth gate having three inputs and an output, and a fifth gate having two inputs and output, said clock signal terminal being connected to one of the inputs of said third gate and to one of the inputs of said fourth gate, the output of said first-stage logic circuit being connected to another one of the inputs of said third gate and to another one of the inputs of said fourth gate, the output of said third gate being connected to still another one on the inputs of said fourth gate and to another one of the inputs of said fifth gate.

Claim 6

A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, a second clock signal input terminal for receiving a second clock signal, noninverting output terminal, and an inverted signal output terminal; means for providing an enable signal, first and second data signals and a test data signal such that said enable signal has a first constant value when said first input data or said second input data is received, and said enable signal has a second constant value when said test data is received, said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal, and the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal.

Claim 7

A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, a second clock signal input terminal for receiving a second clock signal, noninverting output terminal, and an inverted signal output terminal; means for providing an enable signal, first and second data signals and a test data signal such that said enable signal has a first constant value when said first input data or said second input data is received, and said enable signal has a second constant value when said test data is received, said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal, and the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal.

Claim 8

A logic circut as set forth in claim 5, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal.

Claim 9

A logic circuit as set forth in claim 6, wherein said first-stage logic circuit comprises: a first gate having four inputs respectively connected to said noninverted signal output terminal, to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit; a second gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit; a third gate having three inputs respectively connected to said test data terminal, to said enable terminal through an inverter, and to said one of the outputs of said pre-stage logic circuit; and a fourth gate having three inputs respectively connected to the outputs of said first, second and third gates, and having an output connected to said input of said second-stage logic circuit.

Claim 10

A logic circuit as set forth in claim 6, wherein said final-stage logic circuit comprises cross-coupled first and second gates, and said pre-stage logic circuit comprises a third gate having three inputs and an output, a fourth gate having four inputs and an output, and a fifth gate having two inputs and an output, said first and second clock signal terminals respectively being connected to two of the inputs of said third gate and to two of the inputs of said fourth gate, the output of said first-stage logic circuit being connected to another one of the inputs of said third gate and to another one of the inputs of said fourth gate, the output of said third gate being connected to still another one of the inputs of said fourth gate and to another one of the inputs of said fifth gate.

Claim 11

A logic circuit as set forth in claim 1 comprising a synchronous logic unit including a plurality of flip-flops, each of said flip-flops being constituted by said J-K flip-flop, all of said clock signal terminals being commonly connected, and all of said enable terminals being commonly connected.

Claim 12

A logic circuit as set forth in claim 5 comprising an asynchronous logic unit including a plurality of flip-flops, each of said flip-flops being constituted by said J-K flip-flop, all of said second clock signal terminals being commonly connected, and all of said enable terminals being commonly connected.

Claim 13

A logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a clock signal input terminal for receiving a clock signal, a noninverted signal output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to inputs of the final-shape logic circuit, and the outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said first-stage logic circuit further comprises a first gate having four inputs respectively connected to said noninverted signal output terminal, to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit, a second gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit, a third gate having three inputs respectively connected to said test data terminal, to said enable terminal through an inverter, and to said one of the outputs of said pre-stage logic circuit, and a fourth gate having three inputs respectively connected to the outputs of said first, second and third gates and having an output connected to said input of said second-stage logic circuit; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal.

Claim 14

A logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a clock signal input terminal for receiving a clock signal, a noninverted signal output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to inputs of the final-shape logic circuit, and the outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said first-stage logic circuit further comprises a first gate having four inputs respectively connected to said noninverted signal output terminal, to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit, a second gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit, a third gate having three inputs respectively connected to said test data terminal, to said enable terminal through an inverter, and to said one of the outputs of said pre-stage logic circuit, and a fourth gate having three inputs respectively connected to the outputs of said first, second and third gates and having an output connected to said input of said second-stage logic circuit; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal.

Claim 15

A logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising: a first-stage logic circuit having a first input terminal receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a clock signal input terminal for receiving a clock signal, a noninverted signal output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said final-stage logic circuit comprises cross-coupled first and second gates, and said pre-stage logic circuit comprises a third gate having two inputs and an output, a fourth gate having three inputs and an output, and a fifth gate having two inputs and an output, said clock signal terminal being connected to one of the inputs of said third gate and to one of the inputs of said fourth gate, the output of said first-stage logic circuit being connected to another one of the inputs of said third gate and to another one of the inputs of said fourth gate, the output of said third gate being connected to still another one of the inputs of said forth gate and to another one of the inputs of said fifth gate; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal.

Claim 16

A logic circuit having a test data loading function, comprising at least one J-K flip-flop; said J-K flip flop comprising: a first-stage logic circuit having a first input terminal receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a clock signal input terminal for receiving a clock signal, a noninverted signal output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, the outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said final-stage logic circuit comprises cross-coupled first and second gates, and said pre-stage logic circuit comprises a third gate having two inputs and an output, a fourth gate having three inputs and an output, and a fifth gate having two inputs and an output, said clock signal terminal being connected to one of the inputs of said third gate and to one of the inputs of said fourth gate, the output of said first-stage logic circuit being connected to another one of the inputs of said third gate and to another one of the inputs of said fourth gate, the output of said third gate being connected to still another one of the inputs of said forth gate and to another one of the inputs of said fifth gate; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected data being latched in said second-stage logic circuit in response to said clock signal applied to said clock signal terminal.

Claim 17

A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, a second clock signal input terminal for receiving a second clock signal, noninverting output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said first-stage logic circuit further comprises a first gate having four inputs respectively connected to said noninverted signal output terminal, to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit, a second gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit; a third gate having three inputs respectively connected to said test data terminal, to said enable terminal through an invertor, and to said one of the outputs of said pre-stage logic circuit, and a fourth gate having three inputs respectively connected to the outputs of said first, second and third gates, and having an output connected to said input of said second-stage logic circuit; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal, and the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal.

Claim 18

A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, a second clock signal input terminal for receiving a second clock signal, noninverting output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said first-stage logic circuit further comprises a first gate having four inputs respectively connected to said noninverted signal output terminal, to said second input terminal through an inverter, to said enable terminal, and to one of the outputs of said pre-stage logic circuit, a second gate having four inputs respectively connected to said first input terminal, to said enable terminal, to said inverted signal output terminal, and to said one of the outputs of said pre-stage logic circuit; a third gate having three inputs respectively connected to said test data terminal, to said enable terminal through an invertor, and to said one of the outputs of said pre-stage logic circuit, and a fourth gate having three inputs respectively connected to the outputs of said first, second and third gates, and having an output connected to said input of said second-stage logic circuit; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal, and the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal.

Claim 19

A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, a second clock signal input terminal for receiving a second clock signal, noninverting output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said final-stage logic circuit comprises cross-coupled first and second gates, and said pre-stage logic circuit comprises a third gate having three inputs and an output, a fourth gate having four inputs and an output, and a fifth gate having two inputs and an output, said first and second clock signal terminals respectively being connected to two of the inputs of said third gate and to two of the inputs of said fourth gate, the output of said first-stage logic circuit being connected to another one of the inputs of said third gate and to another one of the inputs of said fourth gate, the output of said third gate being connected to still another one of the inputs of said fourth gate and to another one of the inputs of said fifth gate; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal, and the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal.

Claim 20

A logic circuit having a test data loading function comprising at least one J-K flip-flop; said J-K flip-flop comprising: a first-stage logic circuit having a first input terminal for receiving a first input data, a second input terminal for receiving a second input data, a test data terminal for receiving a test data, an enable terminal for receiving an enable signal, and an output; and a second-stage logic circuit having an input connected to the output of said first-stage logic circuit and further having a first clock signal input terminal for receiving a first clock signal, a second clock signal input terminal for receiving a second clock signal, noninverting output terminal, and an inverted signal output terminal, wherein said second-stage logic circuit comprises a pre-stage logic circuit and a final-stage logic circuit, the output of said first-stage logic circuit being connected to an input of said pre-stage logic circuit, outputs of said pre-stage logic circuit being connected to inputs of said final-stage logic circuit, and outputs of said final-stage logic circuit being respectively connected to said noninverted signal output terminal and to said inverted signal output terminal; said final-stage logic circuit comprises cross-coupled first and second gates, and said pre-stage logic circuit comprises a third gate having three inputs and an output, a fourth gate having four inputs and an output, and a fifth gate having two inputs and an output, said first and second clock signal terminals respectively being connected to two of the inputs of said third gate and to two of the inputs of said fourth gate, the output of said first-stage logic circuit being connected to another one of the inputs of said third gate and to another one of the inputs of said fourth gate, the output of said third gate being connected to still another one of the inputs of said fourth gate and to another one of the inputs of said fifth gate; said first-stage logic circuit operatively selecting, in response to said enable signal applied to said enable terminal, either of said test data or said first and second input data, the selected input data being latched in said second-stage logic circuit in response to said first clock signal applied to said first clock signal terminal, and the selected test data being latched in said second-stage logic circuit in response to said second clock signal applied to said second clock signal terminal.