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US4736319A
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Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses
Assignee: International Business Machines Corp
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Filing: 1985-05-15
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Granted: 1988-04-05
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Expires: 2005-05-15
Abstract
Abstract A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.
Inventors
- 👤 Sumit Dasgupta
- 👤 John M. Hancock
- 👤 James H. Kukula
- 👤 Roger E. Peo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:01
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F13/00; G06F13/14; G06F13/20; G06F13/24
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
310 words
In a multiprocessing system, the combination comprising: a global bus having a plurality of interrupt lines; an executive processor connected to said global bus for signalling interrupt requests on predetermined interrupt lines; a plurality of cells connected to said global bus, each cell being connected to receive an interrupt request from a different one of said predetermined interrupt lines; each cell comprising a cell bus having a plurality of interrupt lines, and a plurality of cell processors each connected to a different one of said interrupt lines of said cell bus for receiving interrupt requests therefrom one cell processor is a master processor for receiving interrupt requests initiated by said executive processor, and each other cell processor in a cell is a slave processor for receiving interrupt requests from said master processor; the total number of cell processors exceeding the number of interrupt lines in said global bus, whereby each cell processor has a unique interrupt by virtue of each cell being connected to a different interrupt line in said global bus and each cell processor being connected to a different interrupt line in said cell bus connected thereto; said executive processor initiating an interrupt request for a given slave processor in one of said cells, such interrupt request being transmitted over said global bus by the one of said interrupt lines thereof connected to said one cell, to said master processor in such cell, said master processor in such cell responding to receipt of such interrupt request to transmit such interrupt request to said given slave processor; and memory means connected to the global bus and each of said cell processors for storing interrupt handling routines; each cell processor in response to an interrupt request received on an interrupt line of said cell bus connected thereto, to interrupt its current processing and process one of said interrupt handling routines.
Claim 2
Dependent Claim
310 words
In a multiprocessing system, the combination comprising: a global bus having a plurality of interrupt lines; an executive processor connected to said global bus for signalling interrupt requests on predetermined interrupt lines; a plurality of cells connected to said global bus, each cell being connected to receive an interrupt request from a different one of said predetermined interrupt lines; each cell comprising a cell bus having a plurality of interrupt lines, and a plurality of cell processors each connected to a different one of said interrupt lines of said cell bus for receiving interrupt requests therefrom one cell processor is a master processor for receiving interrupt requests initiated by said executive processor, and each other cell processor in a cell is a slave processor for receiving interrupt requests from said master processor; the total number of cell processors exceeding the number of interrupt lines in said global bus, whereby each cell processor has a unique interrupt by virtue of each cell being connected to a different interrupt line in said global bus and each cell processor being connected to a different interrupt line in said cell bus connected thereto; said executive processor initiating an interrupt request for a given slave processor in one of said cells, such interrupt request being transmitted over said global bus by the one of said interrupt lines thereof connected to said one cell, to said master processor in such cell, said master processor in such cell responding to receipt of such interrupt request to transmit such interrupt request to said given slave processor; and memory means connected to the global bus and each of said cell processors for storing interrupt handling routines; each cell processor in response to an interrupt request received on an interrupt line of said cell bus connected thereto, to interrupt its current processing and process one of said interrupt handling routines.
Claim 3
Dependent Claim
59 words
The combination of claim 1 comprising bus interface means interconnecting said global bus with each cell bus, said bus interface means comprising interrupt handling means for receiving an interrupt request from said global bus and interrupt means connected to said cell busses for placing such interrupt request on an interrupt line of such cell for interrupting said master processor.
Claim 4
Dependent Claim
64 words
The combination of claim 2, wherein said bus interface means includes means responsive to the receipt of an interrupt request from said global bus to send and acknowledgement of said executive processor and allow said executive procesor to proceed with further processing while said interrupt request is being processed by said bus interface means and said cell to which the interrupt request is directed.
Claim 5
Dependent Claim
140 words
The combination of claim 3 wherein: said memory means comprises: a plurality of local memories connected to a different one of said cell processors each storing said interrupt handling routines, and a plurality of interface memories connected between each of said cell busses and said global bus, said executive processor transferring a message through said global bus into the one of said interface memories connected with the given cell to which an interrupt request is directed, said message defining what work is to be done as a result of an interrupt request, said master processor having an interrupt handling routine in said local memory connected thereto which handling routine is to respond to said interrupt request on said global bus, to interpret said message, and to signal an interrupt request on said cell bus to one of said cell processors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-05 | 1991-10-05 | 1992-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-05 | 1995-10-05 | 1996-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-05 | 1999-10-05 | 2000-04-05 | $7700.00 | Window Closed / Lapsed |