US4376973A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital data processing apparatus
Assignee: UK Secretary of State for Defence
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Filing: 1980-02-08
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Granted: 1983-03-15
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Expires: 2000-02-08
Abstract
Abstract A modular data processing unit is adapted to form part of a processing system comprising a plurality of such processing units connected in master-slave relationship. Each processing unit comprises a control section responsive to a control instruction to perform the execution of a program stored therein and to switch the processing unit to an idle mode on completion of the program execution, an internal memory section including an area of read/write memory; a computation section for performing calculations in accordance with the program instructions during which it can access the internal memory; and interface means through which the processor unit can be connected as a master unit to one or more slave units to monitor and control, and to access the internal memories of the slave units while it is executing a program, and through which it can be connected as a slave to a master processing unit by which it can thus be monitored and controlled, and have its internal read/write memory accessed. In such a multi-processor system, a master unit may be connected to a number of slave units each programmed to carry out a particular function, and in turn each of these slave units may be connected as a master to its own set of slave units, again each programmed to perform a particular function; the whole system being coordinated and controlled by the original master unit.
Inventors
- 👤 Howard R. Chivers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 11:47
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F15/16; G06F15/163
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
440 words
A data processing unit comprising: a control section responsive to a control instruction to switch the processing unit from an idle mode to an execution mode, the control section being operative during the execution mode to initiate and control the sequence of execution of a program stored therein and to automatically switch the processing unit to the idle mode in which the control section is no longer operative to initiate and control the sequence of execution of a program stored therein, a memory section including an area of read/write memory, a computation section for performing calculations in accordance with instructions from the program and capable of accessing the read/write memory area during execution of the program, interface means having access to the area of read/write memory through which the processing unit is able to access an external memory when in its execution mode, through which at least part of the read/write memory area of the processing unit is able to be accessed from outside when in its idle mode and through which said control instruction for switching the processing unit from its idle to its execution mode is able to be received from outside; a predetermined part of the read/write memory area of the memory section which is accessible from outside via the interface means being adapted to receive said control instruction, and the control section including means for responding to the control instruction in the predetermined part of the read/write memory area, the interface means comprising a master interface means including a master address bus through which the processing unit is able to receive address words designating locations in its read/write memory and a master data bus through which the processing unit is able to receive or transmit data to be written into or read from the memory locations designated by said address words, through which a predetermined part of the externally accessible read/write memory area is able to be accessed from outside for control and monitor purposes when the processing unit is in both its idle and execution modes, and through which the remaining part of the externally accessible read/write memory area is able to be accessed from outside only when the processing unit is in its idle mode, and slave interface means including a slave address bus through which the processing unit is able to transmit memory addresses to an external memory area and a slave data bus through which data to be written into or read from the external memory is able to be transmitted or received, through which the processing unit is connectable to access the external memory area only when in its execution mode.
Claim 2
Dependent Claim
440 words
A data processing unit comprising: a control section responsive to a control instruction to switch the processing unit from an idle mode to an execution mode, the control section being operative during the execution mode to initiate and control the sequence of execution of a program stored therein and to automatically switch the processing unit to the idle mode in which the control section is no longer operative to initiate and control the sequence of execution of a program stored therein, a memory section including an area of read/write memory, a computation section for performing calculations in accordance with instructions from the program and capable of accessing the read/write memory area during execution of the program, interface means having access to the area of read/write memory through which the processing unit is able to access an external memory when in its execution mode, through which at least part of the read/write memory area of the processing unit is able to be accessed from outside when in its idle mode and through which said control instruction for switching the processing unit from its idle to its execution mode is able to be received from outside; a predetermined part of the read/write memory area of the memory section which is accessible from outside via the interface means being adapted to receive said control instruction, and the control section including means for responding to the control instruction in the predetermined part of the read/write memory area, the interface means comprising a master interface means including a master address bus through which the processing unit is able to receive address words designating locations in its read/write memory and a master data bus through which the processing unit is able to receive or transmit data to be written into or read from the memory locations designated by said address words, through which a predetermined part of the externally accessible read/write memory area is able to be accessed from outside for control and monitor purposes when the processing unit is in both its idle and execution modes, and through which the remaining part of the externally accessible read/write memory area is able to be accessed from outside only when the processing unit is in its idle mode, and slave interface means including a slave address bus through which the processing unit is able to transmit memory addresses to an external memory area and a slave data bus through which data to be written into or read from the external memory is able to be transmitted or received, through which the processing unit is connectable to access the external memory area only when in its execution mode.
Claim 3
Dependent Claim
137 words
A data processing unit as claimed in claim 1 wherein said predetermined part of the externally accessible read/write memory area is adapted to be accessed both from outside via the master interface means and by the control section during both the idle and the execution modes of the processing unit, and the control section includes means for writing into it data indicating a change in the current activity status, idle or executing, of the processing unit, and for reading from it control instruction data indicating a required change in the activity status, idle or executing, of the processing unit written into said predetermined part of the read/write memory area from outside via the master interface means, whereby to enable the activity status of the processing unit to be monitored and controlled from outside via the interface means.
Claim 4
Dependent Claim
55 words
A processing unit as claimed in claim 2 wherein the activity status of the processing unit is indicated by a one-bit binary work location in said predetermined part of the read/write memory area, one value of which indicates the idle mode and the other value of which indicates the execution mode of the processing unit.
Claim 5
Dependent Claim
112 words
A processing unit as claimed in claim 2 or claim 3 wherein the control section is capable of controlling the execution of either one or one of a plurality of programs the sequential instructions of which are stored in programmable read only memory (PROM), each program having a different starting address within the PROM, the predetermined part of externally accessible read/write memory area including a memory location into which control instruction data indicating the starting address of one of said programs can be written from outside via the master interface means as part of said control instruction, and from which this data can be read by the control section for program selection.
Claim 6
Dependent Claim
30 words
A data processing unit as claimed in claim 1, 2 or 3 wherein said predetermined part of the externally accessible read/write memory area is provided by a separate memory device.
Claim 7
Dependent Claim
40 words
A data processing unit as claimed in claim 1 wherein the external memory address capacity of the unit via the slave interface means is substantially greater than the internal read/write memory area accessible from outside via the master interface means.
Claim 8
Dependent Claim
87 words
A data processing system comprising a plurality of data processing units each as claimed in claim 1 wherein the slave interface means of a first of said processing units is connected to the master interface means of each of one or more other processing units, whereby the first processing unit, when in its execution mode, is able to access the externally accessible internal read/write memory area of the or each of the other processing units which effectively constitute an external memory area for the first processing unit.
Claim 9
Dependent Claim
76 words
A data processing system as claimed in claim 7 wherein the slave interface means of at least one of said other processing units is connected to the master interface means of at least one further processing unit individually associated with it, whereby the externally accessible internal read/write memory area of the or each of said other processing units effectively constitutes an external memory area accessible to the said other processing unit to which it is connected.
Claim 10
Dependent Claim
61 words
A data processing system as claimed in claim 7 or 8 wherein the externally accessible internal read/write memory areas of processing units which have their master interface means connected to the slave interface means of a common processing unit each constitute a separately identifiable section of the external memory address capacity of the common processing unit to which they are connected.
Claim 11
Dependent Claim
138 words
A data processing system as claimed in claims 7 or 8 wherein the interconnection between any processing units which have their master interface means connected to the slave interface means of a common processing unit comprises a commmon address bus through which the common processing unit is able to transmit address words designating memory locations in the externally accessible read/write memory areas of the processing units to which its slave interface means is connected, and the master interface means of each of said processing units includes means for decoding said address words to determine whether the designated memory location lies within its internal read/write memory area, the interconnection further comprising a common data bus through which the common processing unit is able to write data into or read data from the memory locations designated by the address words.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-03-14 | 1986-09-13 | 1987-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-03-14 | 1990-09-13 | 1991-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-03-14 | 1994-09-13 | 1995-03-15 | $7700.00 | Window Closed / Lapsed |