Data processing system having pyramidal hierarchy control flow

Claim 2

A data processing system based upon a pyramidal hierarchy of at least three levels having a bus interfacing adjacent levels thereof, comprising: A. a first, highest level including, 1. a store containing a plurality of addressable locations each capable of retaining an instruction word containing an operation code portion defining an operation to be performed, and 2. a sequence controller for addressing said store to selectively retrieve instruction words therefrom and for placing said words on the bus interfacing the first and second levels; B. second and third respectively lower levels each including a plurality of processing units connected in parallel to the bus interfacing the respective level to the next higher level, 1. each of said processing units containing recognition means responsive to the operation code portion of the instruction word on the bus interfacing it with the next higher level to accept only those words containing designated operation code portions, 2. each of said processing units being of a one of two types, an execution processing unit or a translator processing unit,

Claim 3

each of said second and third levels capable of including execution processing units and translator processing units and each having at least one translator processing unit, a. each of said execution processing units responsive to an instruction word recognized thereby to perform the operation specified by that instruction word, and b. each of said translator processing units including means to distinguish between first and second types of instruction words recognized thereby comprising, i. means responsive to the first of the two types of instruction words for transmitting that instruction word to the next lower interface bus without modification, and ii. means responsive to the second of the two types of instruction words for initiating an operation by an associated execution processing unit in accordance with a stored group of additional instruction words, including means to address a store means containing said additional instruction words; and C. addressable store means associated with each of said translator processing units for storing said additional instruction words.

Claim 4

each of said second and third levels capable of including execution processing units and translator processing units and each having at least one translator processing unit, a. each of said execution processing units responsive to an instruction word recognized thereby to perform the operation specified by that instruction word, and b. each of said translator processing units including means to distinguish between first and second types of instruction words recognized thereby comprising, i. means responsive to the first of the two types of instruction words for transmitting that instruction word to the next lower interface bus without modification, and ii. means responsive to the second of the two types of instruction words for initiating an operation by an associated execution processing unit in accordance with a stored group of additional instruction words, including means to address a store means containing said additional instruction words; and C. addressable store means associated with each of said translator processing units for storing said additional instruction words.

Claim 5

The invention in accordance with claim 1 wherein said addressable store means comprises a read-only memory.

Claim 6

The invention in accordance with claim 1 wherein the data processing system includes at least four levels with the lowest level comprised of all execution processing units.

Claim 7

The invention in accordance with claim 1 wherein the recognition means contained within the processing units includes a decoding means.

Claim 8

The invention in accordance with claim 1 wherein said second level includes at least two translator processing units each forming the beginning of a major leg of said hierarchy.

Claim 9

The invention in accordance with claim 5 wherein each of said legs terminates with one or more execution processing units.

Claim 10

The invention in accordance with claim 1 wherein: A. each of the processing units includes means to provide a status signal indicative of its ability to accept an instruction word to the translator processing unit or sequence controller from which it receives instruction words; and B. each of the translator processing units and sequence controller contains, 1. means to receive the status signals from those processing units of the next lower level to which it is connected and to use as an indication signal the state of that status signal, 2. means to interrogate the operation code portion of a retrieved instruction word to determine which next lower level processing unit will receive that instruction word,

Claim 11

means responsive to the determination of the interrogation and to the appropriate status signal to determine the time of changing the instruction word available on the next lower bus.

Claim 12

means responsive to the determination of the interrogation and to the appropriate status signal to determine the time of changing the instruction word available on the next lower bus.

Claim 13

The invention in accordance with claim 7 wherein the means responsive to the determination of the interrogation and to the appropriate status signal responds to a prescribed change in the state of the status signal to effect the change in the instruction word on the next lower bus.

Claim 14

The invention in accordance with claim 8 wherein the prescribed change is one from an indication that the lower processing unit is not busy to one indicating that the unit is busy.

Claim 15

A data processing system based upon a pyramidal hierarchy of at least three levels having a bus interfacing adjacent levels thereof, comprising: A. a first, highest level including, 1. a store containing a plurality of addressable locations each capable of retaining an instruction word containing an operation code portion defining an operation to be performed, and 2. a sequence controller for addressing said store to selectively retrieve instruction words therefrom and for placing said words on the bus interfacing the first and second levels; B. second and third respectively lower levels each including a plurality of processing units connected in parallel to the bus interfacing the respective level to the next higher level, 1. each of said processing units containing recognition means responsive to the operation code portion of the instruction word on the bus interfacing it with the next higher level to accept only those words containing designated operation code portions, 2. each of said processing units being of a one of two types, an execution processing unit or a translator processing unit, to thereby initiate an operation specified by said retrieved additional instruction words.

Claim 16

A data processing system based upon a pyramidal hierarchy of at least three levels having a bus interfacing adjacent levels thereof, comprising: A. a first, highest level including, 1. a store containing a plurality of addressable locations each capable of retaining an instruction word containing an operation code portion defining an operation to be performed, and 2. a sequence controller for addressing said store to selectively retrieve instruction words therefrom and for placing said words on the bus interfacing the first and second levels; B. second and third respectively lower levels each including a plurality of processing units connected in parallel to the bus interfacing the respective level to the next higher level, 1. each of said processing units containing recognition means responsive to the operation code portion of the instruction word on the bus interfacing it with the next higher level to accept only those words containing designated operation code portions, 2. each of said processing units being of a one of two types, an execution processing unit or a translator processing unit, to thereby initiate an operation specified by said retrieved additional instruction words.

Claim 17

The invention in accordance with claim 10 wherein said addressable store means comprises a read-only memory.

Claim 18

The invention in accordance with claim 10 wherein the data processing system includes at least four levels with the lowest level comprised of all execution processing units.

Claim 19

The invention in accordance with claim 10 wherein the recognition means contained within the processing units includes a decoding means.

Claim 20

The invention in accordance with claim 10 wherein said second level includes at least two translator processing units each forming the beginning of a major leg of said hierarchy.

Claim 21

The invention in accordance with claim 14 wherein each of said legs terminates with one or more execution processing units.

Claim 22

The invention in accordance with claim 10 wherein: A. each of the processing units includes means to provide a status signal indicative of its ability to accept an instruction word to the translator processing unit or sequence controller from which it receives instruction words; and B. each of the translator processing units and sequence controller contains,

Claim 23

means to receive the status signals from those processing units of the next lower level to which it is connected and to use as an indication signal the state of that status signal, 2. means to interrogate the operation code portion of a retrieved instruction word to determine which next lower level processing unit will receive that instruction word, 3. means responsive to the determination of the interrogation and to the appropriate status signal to determine the time of changing the instruction word available on the next lower bus.

Claim 24

means to receive the status signals from those processing units of the next lower level to which it is connected and to use as an indication signal the state of that status signal, 2. means to interrogate the operation code portion of a retrieved instruction word to determine which next lower level processing unit will receive that instruction word, 3. means responsive to the determination of the interrogation and to the appropriate status signal to determine the time of changing the instruction word available on the next lower bus.

Claim 25

The invention in accordance with claim 16 wherein the means responsive to the determination of the interrogation and to the appropriate status signal responds to a prescribed change in the state of the status signal to effect the change in the instruction word on the next lower bus.

Claim 26

The invention in accordance with claim 17 wherein the prescribed change is one from an indication that the lower processing unit is not busy to one indicating that the unit is busy.

Claim 27

A data processing system of pyramidal architecture of at least three levels having a bus interfacing adjacent levels thereof, comprising: A. a first, highest level including, 1. a store containing a plurality of addressable locations each capable of retaining an instruction word to be executed, 2. a sequence controller for addressing said store to selectively retrieve first type instruction words therefrom and for placing said words on the bus interfacing the first and second levels, each such instruction word containing an operation code portion defining an operation to be performed and an operand portion defining at least one source of data to be operated upon; and B. second and third respectively lower levels, each including, 1. a plurality of processing units of first and second types connected in parallel to the bus interfacing the respective level with the next higher level, at least one of said units being of the first type and each of said units including means for interrogating an instruction word on the bus interfacing it with the next higher level and for accepting only instruction words containing designated operation code portions, 2. each of said first type of processing unit including means for storing second type instruction words, each second type instruction word defining an operation to be performed, and further including selection means for selectively placing said first and second type instruction words on the bus of the next lower level in accordance with the operation code portion of an instruction word provided thereto from the bus of the next higher level, and 3. each of said second type of processing unit responsive to an instruction word accepted thereby to execute the instruction word as specified by the operation code portion of that instruction word by selectively performing an operation whereby that selected operation is performed on data defined by the operand portion of a first type instruction when so specified by the operation code portion of the instruction being executed.

Claim 28

A data processing system of pyramidal architecture of at least three levels having a bus interfacing adjacent levels thereof, comprising: A. a first, highest level including, 1. a store containing a plurality of addressable locations each capable of retaining an instruction word to be executed, 2. a sequence controller for addressing said store to selectively retrieve first type instruction words therefrom and for placing said words on the bus interfacing the first and second levels, each such instruction word containing an operation code portion defining an operation to be performed and an operand portion defining at least one source of data to be operated upon; and B. second and third respectively lower levels, each including, 1. a plurality of processing units of first and second types connected in parallel to the bus interfacing the respective level with the next higher level, at least one of said units being of the first type and each of said units including means for interrogating an instruction word on the bus interfacing it with the next higher level and for accepting only instruction words containing designated operation code portions, 2. each of said first type of processing unit including means for storing second type instruction words, each second type instruction word defining an operation to be performed, and further including selection means for selectively placing said first and second type instruction words on the bus of the next lower level in accordance with the operation code portion of an instruction word provided thereto from the bus of the next higher level, and 3. each of said second type of processing unit responsive to an instruction word accepted thereby to execute the instruction word as specified by the operation code portion of that instruction word by selectively performing an operation whereby that selected operation is performed on data defined by the operand portion of a first type instruction when so specified by the operation code portion of the instruction being executed.

Claim 29

A data processing system of pyramidal architecture having at least three levels, each higher level having a bus interfacing it with the next lower level, comprising: A. a first, highest level including,

Claim 30

A data processing system of pyramidal architecture having at least three levels, each higher level having a bus interfacing it with the next lower level, comprising: A. a first, highest level including,

Claim 31

a store containing a plurality of addressable locations each capable of retaining an instruction word to be executed, 2. a sequence controller for placing a first type instruction word on the bus interfacing the first and second levels, each such instruction word containing an operation code portion defining at least one operation to be performed and an operand portion including a field defining at least one source of data to be operated upon; and B. second and third respectively lower levels, each including, 1. a plurality of processing units of first and second types connected in parallel to the bus interfacing the respective level to the next higher level, at least one of said units being of said first type, each of said processing units capable of accepting only an instruction word containing an operation code portion of a prescribed content, a. each of said first type of processing units including means for storing second type instruction words, each of said second type instruction words comprised of an operation code portion defining an operation to be performed, said first type processing unit further including recognition selection means for selectively placing an instruction word on the bus of the next lower level in accordance with the operation code portion of an instruction provided thereto from the bus of the next higher level, b. each of said second types of processing units selectively responsive to said first and second types of instruction words accepted thereby to execute an instruction as specified by the operation code portion of that instruction by selectively performing an operation whereby that selected operation is performed on data defined by the field of the operand portion of a first type instruction when so specified by the operation code portion of the instruction being executed.

Claim 32

a store containing a plurality of addressable locations each capable of retaining an instruction word to be executed, 2. a sequence controller for placing a first type instruction word on the bus interfacing the first and second levels, each such instruction word containing an operation code portion defining at least one operation to be performed and an operand portion including a field defining at least one source of data to be operated upon; and B. second and third respectively lower levels, each including, 1. a plurality of processing units of first and second types connected in parallel to the bus interfacing the respective level to the next higher level, at least one of said units being of said first type, each of said processing units capable of accepting only an instruction word containing an operation code portion of a prescribed content, a. each of said first type of processing units including means for storing second type instruction words, each of said second type instruction words comprised of an operation code portion defining an operation to be performed, said first type processing unit further including recognition selection means for selectively placing an instruction word on the bus of the next lower level in accordance with the operation code portion of an instruction provided thereto from the bus of the next higher level, b. each of said second types of processing units selectively responsive to said first and second types of instruction words accepted thereby to execute an instruction as specified by the operation code portion of that instruction by selectively performing an operation whereby that selected operation is performed on data defined by the field of the operand portion of a first type instruction when so specified by the operation code portion of the instruction being executed.

Claim 33

The invention in accordance with claim 20 wherein the field of the operand portion of the first type instruction word defines a plurality of sources of data to be operated upon and wherein the second type of processing units perform operations defined by at least one of the plurality of sources.

Claim 34

A data processing system of pyramidal architecture having at least three levels consecutively defining highest to lowest levels, each level having an instruction bus for the interconnection of adjacent levels thereof comprising: A. a sequence controller including a store, said controller containing means for retrieving an instruction word retained in said store and for placing a retrieved word on the highest level bus serving to interconnect the first and second levels, said instruction word containing an operation code portion defining an operation to be performed and an operand portion defining data to be operated on; B. a first plurality of processing units connected in parallel between the buses of the first and second levels, and a second plurality of processing units connected in parallel to at least one bus of the third level whereby each processing unit interfaces with the bus of the next higher level, said processing units being of two types, execution processing units and translator processing units, at least one of said processing units connected between the buses of the first and second levels being a translator processing unit, 1. each of said processing units including storage means for temporarily storing an instruction word provided thereto from the bus interfacing it with the next higher level, 2. each of said processing units including recognition means responsive to the operation code portion of the instruction word stored in its storage means to accept only instruction words containing designated operation codes, 3. each of said translator processing units comprising, a. an addressable store for storing at least one group of additional instruction words, each defining an operation to be performed, said addressable store being addressable from the operation code portion of the instruction word in said translator processing unit's storage means at a location therein containing the first instruction word of a group of words, b. means responsive to the operation code portion of the instruction word in said translator processing unit's storage means to sequentially retrieve words of an identified group from said addressable store to thereby sequentially place the retrieved instruction words on the bus of the next lower level to effect an operation in at least one processing unit at a lower level responsible for each of the instruction words so retrieved, and

Claim 35

A data processing system of pyramidal architecture having at least three levels consecutively defining highest to lowest levels, each level having an instruction bus for the interconnection of adjacent levels thereof comprising: A. a sequence controller including a store, said controller containing means for retrieving an instruction word retained in said store and for placing a retrieved word on the highest level bus serving to interconnect the first and second levels, said instruction word containing an operation code portion defining an operation to be performed and an operand portion defining data to be operated on; B. a first plurality of processing units connected in parallel between the buses of the first and second levels, and a second plurality of processing units connected in parallel to at least one bus of the third level whereby each processing unit interfaces with the bus of the next higher level, said processing units being of two types, execution processing units and translator processing units, at least one of said processing units connected between the buses of the first and second levels being a translator processing unit, 1. each of said processing units including storage means for temporarily storing an instruction word provided thereto from the bus interfacing it with the next higher level, 2. each of said processing units including recognition means responsive to the operation code portion of the instruction word stored in its storage means to accept only instruction words containing designated operation codes, 3. each of said translator processing units comprising, a. an addressable store for storing at least one group of additional instruction words, each defining an operation to be performed, said addressable store being addressable from the operation code portion of the instruction word in said translator processing unit's storage means at a location therein containing the first instruction word of a group of words, b. means responsive to the operation code portion of the instruction word in said translator processing unit's storage means to sequentially retrieve words of an identified group from said addressable store to thereby sequentially place the retrieved instruction words on the bus of the next lower level to effect an operation in at least one processing unit at a lower level responsible for each of the instruction words so retrieved, and

Claim 36

each of said execution processing units responsive to an instruction word retrieved from a translator processing unit of the next higher level and recognized thereby to perform the operation specified by that instruction word on data defined by the operand portion of the instruction word retrieved by said sequence controller.

Claim 37

each of said execution processing units responsive to an instruction word retrieved from a translator processing unit of the next higher level and recognized thereby to perform the operation specified by that instruction word on data defined by the operand portion of the instruction word retrieved by said sequence controller.