Fault detection circuit

Claim 2

Fault detection circuit comprising: output driver means having a control terminal and at least one output terminal, current through said output driver means determined by signal magnitude at said control terminal; load means having first and second end terminals, said second end terminal coupled to said output terminal such that currrent through said output driver means determines current through said load means; current sense resistor means connected in series with said load means by being coupled between said first end terminal and a fixed reference potential such that current through said resistor means normally corresponds to current through said load means; current control means coupled to said resistor means for, in response to receiving an enable signal having signal transitions to a predetermined logic state, controlling signal magnitude at said control terminal in accordance with current through said resistor means to effectively provide at least a predetermined minimum current level through said load means during said logic state; wherein the improvement comprises, fault detection means coupled to said load means for detecting short circuits to said fixed reference potential present at either of said first and second end terminals and providing separate fault detection signals in response thereto; and fault control means coupled to said fault detection means for altering signal magnitude at said control terminal, in response to said fault detection signals, so as to effectively reduce current through at least one of said output driver means and said load means to prevent damage thereto in the event of a short circuit at any of said end terminals.

Claim 3

Fault detection circuit according to claim 1 wherein said fault detection means includes first means for providing a first one of said fault detection signals in response to determining current through said load means being less than said predetermined minimum current level after a first predetermined delay time after said transition of said enable signal to said predetermined logic state.

Claim 4

Fault detection circuit according to claim 2 wherein said first means includes comparator means for monitoring the voltage at said first end terminal and effectively comparing it to a predetermined first reference voltage, and means for providing said first one of said fault detection signals in accordance with an output of said comparator means after said first delay time.

Claim 5

Fault detection circuit according to claim 3 wherein said current control means provides switching of said output driver means on and off during said predetermined logic state to control load current between limits, and wherein said fault detection means includes second means for effectively monitoring the voltage at said second end terminal and comparing it to a predetermined second reference voltage, said second means providing a second one of said fault detection signals in accordance with said comparison of said second end terminal voltage after a predetermined second delay time after each switching of said output driver means by said current control means to a predetermined operative state.

Claim 6

Fault detection circuit according to claim 4 wherein said first delay time substantially exceeds said second delay time.

Claim 7

Fault detection circuit according to claim 4 wherein each of said first and second ones of said fault detection signals result in setting an output of a latch means in said fault control means to a predetermined state, said predetermined state implementing said current reduction.

Claim 8

Fault detection circuit according to claim 1 wherein said current control means provides switching of said output driver means on and off during said predetermined logic state to control load current between limits, and wherein said fault detection means includes means for effectively monitoring the voltage at said second end terminal and comparing it to a predetermined reference voltage, said fault detection providing one of said fault detections signals in accordance with said comparison after a predetermined delay time after each switching of said output driver means by said current control means to a predetermined operative state.

Claim 9

Fault detection circuit according to claim 1 wherein said output driver means is coupled in series with said load means and said resistor means such that each has substantially the same through current in the absence of short circuits at said first and second end terminals.

Claim 10

Fault detection circuit according to claim 1 wherein said fault control means includes latch means which is set to a predetermined state for implementing said current reduction in response to said fault detection signals.

Claim 11

Fault detection circuit according to claim 8 wherein said current control means includes means for providing a switching excitation signal at said control terminal, predetermined transitions in said excitation signal normally commencing current flow through said output driver means, and wherein said latch means is periodically reset in response to transitions in said enable signal.

Claim 12

Fault detection circuit for a fuel injector driver comprising: output driver means having a control terminal and at least one output terminal, current through said output driver means determined by signal magnitude at said control terminal; load means, comprising a fuel injector solenoid coil, having first and second end terminals, said second end terminal coupled to said output terminal such that current through said output driver means determines current through said load means; current sense resistor means connected in series with said load means by being coupled between said first end terminal and a fixed reference potential such that current through said resistor menas normally corresponds to current through said load means; current control means coupled to said resistor means for, in response to receiving an enable signal having signal transitions to a predetermined logic state, controlling signal magnitude at said control terminal in accordance with current through said resistor means to effectively provide at least a predetermined minumum current level through said load means during said logic state; wherein the improvement comprises, fault detection means coupled to said load means for detecting short circuits to said fixed reference potential present at either of said first and second end terminals and providing separate fault detection signals in response thereto; and fault control means coupled to said fault detection means for altering signal magnitude at said control terminal, in response to said fault detection signals, so as to effectively reduce current through at least one of said output driver means and said load means to prevent damage thereto in the event of a short circuit at any of said end terminals.

Claim 13

Fault detection circuit for a fuel injector driver comprising: output driver means having a control terminal and at least one output terminal, current through said output driver means determined by signal magnitude at said control terminal; load means, comprising a fuel injector solenoid coil, having first and second end terminals, said second end terminal coupled to said output terminal such that current through said output driver means determines current through said load means; current sense resistor means connected in series with said load means by being coupled between said first end terminal and a fixed reference potential such that current through said resistor menas normally corresponds to current through said load means; current control means coupled to said resistor means for, in response to receiving an enable signal having signal transitions to a predetermined logic state, controlling signal magnitude at said control terminal in accordance with current through said resistor means to effectively provide at least a predetermined minumum current level through said load means during said logic state; wherein the improvement comprises, fault detection means coupled to said load means for detecting short circuits to said fixed reference potential present at either of said first and second end terminals and providing separate fault detection signals in response thereto; and fault control means coupled to said fault detection means for altering signal magnitude at said control terminal, in response to said fault detection signals, so as to effectively reduce current through at least one of said output driver means and said load means to prevent damage thereto in the event of a short circuit at any of said end terminals.

Claim 14

Fault detection circuit for a fuel injector driver according to claim 11 wherein said fault detection means includes first means for providing a first one of said fault detection signals in response to determining current through said load means being less than said predetermined minimum current level after a first predetermined delay time after said transition of said enable signal to said predetermined logic state.

Claim 15

Fault detection circuit for a fuel injector driver according to claim 12 wherein said first means includes comparator means for monitoring the voltage at said first end terminal and effectively comparing it to a predetermined first reference voltage, and means for providing said first one of said fault detection signals in accordance with an output of said comparator means after said first delay time.

Claim 16

Fault detection circuit for a fuel injector driver according to claim 13 wherein said current control means provides switching of said output driver means on and off during said predetermined logic state to control load current between limits, and wherein said fault detection means includes second means for effectively monitoring the voltage at said second end terminal and comparing it to a predetermined second reference voltage, said second means providing a second one of said fault detection signals in accordance with said comparison of said second end terminal voltage after a predetermined second delay time after each switching of said output driver means by said current control means to a predetermined operative state.

Claim 17

Fault detection circuit for a fuel injector driver according to claim 14 wherein said first delay time substantially exceeds said second delay time.

Claim 18

Fault detection circuit for a fuel injector driver according to claim 14 wherein each of said first and second ones of said fault detection signals result in setting an output of a latch means in said fault control means to a predetermined state, said predetermined state implementing said current reduction.

Claim 19

Fault detection circuit for a fuel injector driver according to claim 11 wherein said current control means provides switching of said output driver means on and off during said predetermined logic state to control load current between limits, and wherein said fault detection means includes means for effectively monitoring the voltage at said second end terminal and comparing it to a predetermined reference voltage, said fault detection providing one of said fault detections signals in accordance with said comparison after a predetermined delay time after each switching of said output driver means by said current control means to a predetermined operative state.

Claim 20

Fault detection circuit for a fuel injector driver according to claim 11 wherein said output driver means is coupled in series with said load means and said resistor means such that each has substantially the same through current in the absence of short circuits at said first and second end terminals

Claim 21

Fault detection circuit for a fuel injector driver according to claim 11 wherein said fault control means includes latch means which is set to a predetermined state for implementing said current reduction in response to said fault detection signals.

Claim 22

Fault detection circuit for a fuel injector driver according to claim 18 wherein said current control means includes means for providing a switching excitation signal at said control terminal, predetermined transitions in said excitation signal normally commencing current flow through said output driver means, and wherein said latch means is periodically reset in response to transitions in said enable signal.

Claim 23

Fault detection circuit comprising: output driver means having a control terminal and at least one output terminal, current through said output driver means determined by signal magnitude at said control terminal; load means coupled to said output terminal such that current through said output driver means determines current through said load means; current sense resistor means coupled to said load means such that current through said resistor means normally corresponds to current through said load means; current control means coupled to said resistor means for, in response to receiving an enable signal having signal transitions to a predetermined logic state, controlling signal magnitude at said control terminal in accordance with current through said resistor means to effectively provide at least a predetermined minimum current level through said load means during said logic state; wherein the improvement comprises, fault detection means coupled to said load means and said current sense resistor means for detecting short circuits by effectively monitoring, during said logic state, the voltage applied across the load means and the current through the load means and providing separate first and second fault detection signals in response to either current through said load means being less than said predetermined minimum current level after a first predetermined delay time after said transition of said enable signal to said predetermined logic state or the voltage applied across said load being below a predetermined level, respectively; and fault control means coupled to said fault detection means for altering signal magnitude at said control terminal, in response to said fault detection signals, so as to effectively reduce current through at least one of said output driver means and said load means to prevent damage thereto in the event of a short circuit.

Claim 24

Fault detection circuit comprising: output driver means having a control terminal and at least one output terminal, current through said output driver means determined by signal magnitude at said control terminal; load means coupled to said output terminal such that current through said output driver means determines current through said load means; current sense resistor means coupled to said load means such that current through said resistor means normally corresponds to current through said load means; current control means coupled to said resistor means for, in response to receiving an enable signal having signal transitions to a predetermined logic state, controlling signal magnitude at said control terminal in accordance with current through said resistor means to effectively provide at least a predetermined minimum current level through said load means during said logic state; wherein the improvement comprises, fault detection means coupled to said load means and said current sense resistor means for detecting short circuits by effectively monitoring, during said logic state, the voltage applied across the load means and the current through the load means and providing separate first and second fault detection signals in response to either current through said load means being less than said predetermined minimum current level after a first predetermined delay time after said transition of said enable signal to said predetermined logic state or the voltage applied across said load being below a predetermined level, respectively; and fault control means coupled to said fault detection means for altering signal magnitude at said control terminal, in response to said fault detection signals, so as to effectively reduce current through at least one of said output driver means and said load means to prevent damage thereto in the event of a short circuit.

Claim 25

Fault detection circuit according to claim 21 wherein said fault detection means includes comparator means for effectively monitoring the voltage across said current sensing means and effectively comparing it to a predetermined first reference voltage, and means for providing said first fault detection signal in accordance with an output of said comparator means after said first delay time.

Claim 26

Fault detection circuit according to claim 22 wherein said current control means provides switching of said output driver means on and off during said predetermined logic state to control load current between limits, and wherein said fault detection means includes means for effectively monitoring the voltage across said load means and comparing it to a predetermined second reference voltage, and for providing said second fault detection signal in accordance with said comparison of said voltage across said load means after a predetermined second delay time after each switching of said output driver means by said current control means to a predetermined operative state.

Claim 27

Fault detection circuit according to claim 23 wherein said first delay time substantially exceeds said second delay time.

Claim 28

Fault detection circuit according to claim 24 wherein each of said first and second fault detection signals result in setting an output of a latch means in said fault control means to a predetermined state, said predetermined state implementing said current reduction.

Claim 29

Fault detection circuit according to claim 21 wherein said current control means provides switching of said output driver means on and off during said predetermined logic state to control load current between limits, and wherein said fault detection means includes means for effectively monitoring the voltage across said load means and comparing it to a predetermined second reference voltage, and for providing said second fault detection signal in accordance with said comparison of said voltage across said load means after a predetermined second delay time after each switching of said output driver means by said current control means to a predetermined operative state.

Claim 30

Fault detection circuit according to claim 21 wherein said output driver means is coupled in series with said load means and said resistor means such that each has substantially the same through current in the absence of short circuit faults.

Claim 31

Fault detection circuit according to claim 21 wherein said fault control means includes latch means which is set to a predetermined state for implementing said current reduction in response to said fault detection signals.

Claim 32

Fault detection circuit according to claim 28 wherein said latch means is periodically reset in response to transitions in said enable signal.

Claim 33

Fault detection circuit according to claim 21 wherein said load means comprises an inductive load having a substantial inductance.