Electrically programmable semiconductor memory showing redundance

Claim 1

An integrated memory system comprising: an m x n matrix arrangement of memory cells, each memory cell having an electrically floating gate, said memory matrix including: a main memory portion; main decoder means for accessing data stored in said main memory; a first memory portion containing spare rows; first decoder means for accessing said spare rows; a second memory portion wherein addresses of faulty rows in said main memory are stored; and second decoder means for accessing memory rows of said second memory portion; a microcomputer for controlling operation of said memory system; a reference voltage source, said voltage source being adjustable in steps by said microcomputer; a comparator having first inputs receiving first voltage signals derived from the drain currents of the memory transistor of a selected word, said comparator having second inputs coupled to said reference voltage source, said comparator having outputs coupled to said microcomputer; a correction register having outputs coupled to said first decoder means for either transferring addresses to said first decoder means or blocking the operation thereof; storing means coupled to said microcomputer and to said matrix arrangement for storing data in said matrix arrangement; said microcomputer being operable to test for defective rows by transferring data into said main memory via said storing means, reading data stored in said memory and for setting said voltage source, and reading the outputs of said comparator; said microcomputer performing said test for defective rows at predetermined time intervals; said microcomputer storing addresses of defective rows in said second memory portion and storing data for each defective row in a spare row of said first memory portion.

Claim 3

A method of detecting defective rows of an integrated memory matrix comprising the steps of: utilizing a microprocessor to periodically test said matrix; storing predetermined data in rows of said matrix; reading each row of said memory a plurality of times; providing a reference voltage level from a reference voltage cell; comparing the output voltage level of each cell of a row with said reference voltage level from said reference voltage cell to detect defective rows; varying said reference voltage level for each time a row is read out to detect defective rows; storing the address of a defective row in one portion of said matrix; storing the address of each defective row in a correction register; and storing data for a defective row in a selected spare row.

Claim 4

A method of detecting defective rows of an integrated memory matrix comprising the steps of: utilizing a microprocessor to periodically test said matrix; storing predetermined data in rows of said matrix; reading each row of said memory a plurality of times; providing a reference voltage level from a reference voltage cell; comparing the output voltage level of each cell of a row with said reference voltage level from said reference voltage cell to detect defective rows; varying said reference voltage level for each time a row is read out to detect defective rows; storing the address of a defective row in one portion of said matrix; storing the address of each defective row in a correction register; and storing data for a defective row in a selected spare row.