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Method for making a bipolar transistor and capacitors using doped polycrystalline silicon or metal silicide

Assignee: Toshiba Corp
•
Filing: 1985-06-26
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Granted: 1988-03-22
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Expires: 2005-06-26
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Abstract

Abstract The invention provides a method for making a semiconductor device including a bipolar transistor and a capacitor. An oxide film and a silicon nitride film are formed and patterned on a semiconductor substrate. A layer of polycrystalline silicon or of metal silicide containing an impurity is formed between an emitter electrode and an emitter region of the transistor and between an electrode and a thin oxide film of the capacitor. The doped polycrystalline silicon or metal silicide is then patterned to form a barrier layer protecting the oxide film and an intermediate layer acting as a diffusion source to the underlying substrate.

Inventors

  • 👤 Shigeru Komatsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 16:58
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 209 words
A method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate of a first conductivity type having a first impurity region and a second impurity region of a second conductivity type; forming an oxide film on said semiconductor substrate; forming on said oxide film a silicon nitride film having a first opening above said first impurity region and a second opening above said second impurity region; forming a contact hole in said oxide film through said second opening; forming a conductive layer containing an impurity of the first conductivity type, and made of a material selected from the group consisting of polycrystalline silicon and metal silicide, on said silicon nitride film and exposed regions of said oxide film and said substrate; selectivity removing said conductive layer to leave a first portion on said oxide film and a second portion on said substrate, said first portion acting as a barrier layer for protecting said oxide film, and said second portion acting as an intermediate layer; forming a third impurity region of the first conductivity type in said second impurity region by diffusing the impurity of said second portion into said second impurity region; and forming metal electrodes connected to said barrier layer and said intermediate layer.
Claim 2
Independent Claim 209 words
A method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor substrate of a first conductivity type having a first impurity region and a second impurity region of a second conductivity type; forming an oxide film on said semiconductor substrate; forming on said oxide film a silicon nitride film having a first opening above said first impurity region and a second opening above said second impurity region; forming a contact hole in said oxide film through said second opening; forming a conductive layer containing an impurity of the first conductivity type, and made of a material selected from the group consisting of polycrystalline silicon and metal silicide, on said silicon nitride film and exposed regions of said oxide film and said substrate; selectivity removing said conductive layer to leave a first portion on said oxide film and a second portion on said substrate, said first portion acting as a barrier layer for protecting said oxide film, and said second portion acting as an intermediate layer; forming a third impurity region of the first conductivity type in said second impurity region by diffusing the impurity of said second portion into said second impurity region; and forming metal electrodes connected to said barrier layer and said intermediate layer.
Claim 3
Dependent Claim 18 words
A method according to claim 1, wherein said conductive layer has a thickness of 500 to 5,000 Å.

References Cited (Backward Citations)

FR2083346A1 Cited
US4001869A Cited
US4040017A Cited
JPS5336485A Cited
US4145803A Cited
US4282647A Cited
GB2019091A Cited
JPS5586148A Cited
US4377029A Cited
EP0031450A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1991-03-22 1991-09-21 1992-03-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1995-03-22 1995-09-21 1996-03-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1999-03-22 1999-09-21 2000-03-22 $7700.00 Window Closed / Lapsed

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