Patent US4731602A successfully refreshed from Google Patents.
US4731602A
Expired / Lapsed
US
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Converter
Assignee: Sony Corp
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Filing: 1986-09-23
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Granted: 1988-03-15
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Expires: 2006-09-23
Abstract
Abstract An analog-to-digital or digital-to-analog converter comprises: a signal input terminal an integrator connected to the signal input terminal; a plurality of constant current sources connected to the integrator so that the integrator is supplied with respective constant currents; a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and a clock signal generator for generating a first clock signal having a first clock frequency and being supplied to the first counter and a second clock signal having a second frequency higher than the first clock frequency and being supplied to the second counter; and currents of the plurality of constant current sources are respectively determined according to the first and second predetermined numbers of bits and the first and second clock frequencies of the first and second clock signals, respectively.
Inventors
- 👤 Ikuro Hata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:25
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16; H03M1/162; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
150 words
An analog-to-digital converter comprising: a signal input terminal; an integrator connected to said signal input terminal; a plurality of constant current sources connected to said integrator so that said integrator is supplied with respective constant currents; counter means including a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and clock signal generating means for generating a first clock signal having a first clock frequency and being supplied to said first counter and a second clock signal having a second frequency higher than said first clock frequency and being supplied to said second counter; said plurality of constant current sources having respective currents which are determined according to said first and second predetermined numbers of bits and said first and second clock frequencies of said first and second clock signals, respectively.
Claim 2
Dependent Claim
150 words
An analog-to-digital converter comprising: a signal input terminal; an integrator connected to said signal input terminal; a plurality of constant current sources connected to said integrator so that said integrator is supplied with respective constant currents; counter means including a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and clock signal generating means for generating a first clock signal having a first clock frequency and being supplied to said first counter and a second clock signal having a second frequency higher than said first clock frequency and being supplied to said second counter; said plurality of constant current sources having respective currents which are determined according to said first and second predetermined numbers of bits and said first and second clock frequencies of said first and second clock signals, respectively.
Claim 3
Dependent Claim
40 words
An analog-to-digital converter according to claim 1, wherein said clock signal generating means comprises a master clock generating means for generating said first clock signal and frequency doubler means for generating said second clock signal from said first clock signal.
Claim 4
Dependent Claim
21 words
An analog-to-digital converter according to claim 2, wherein said first and second predetermined numbers of bits are equal to each other.
Claim 5
Dependent Claim
255 words
An analog-to-digital converter comprising: an analog signal input terminal; a first switching means; a second switching means; a third switching means; an integrator connected to said analog signal input terminal through said first switching means and having an output; comparator means including a first comparator having a first input terminal connected to said output of the integrator and a second input terminal connected to a first reference voltage source, and a second comparator having a first input terminal connected to said output of said integrator and a second input terminal connected to a second reference voltage source; counter means including a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; clock signal generating means for generating a first clock signal having a first clock frequency and being supplied to said first counter and a second clock signal having a second frequency higher than said first clock frequency and being supplied to said second counter; a plurality of constant current sources connected to said integrator through said second and third switching means, respectively, so that said integrator is supplied with respective constant currents determined according to said first and second predetermined numbers of bits and said first and second clock frequencies of said first and second clock signals, respectively; and control means for controlling said first, second and third switching means and said counter means in response to said clock signal generating means and said comparator means.
Claim 6
Dependent Claim
255 words
An analog-to-digital converter comprising: an analog signal input terminal; a first switching means; a second switching means; a third switching means; an integrator connected to said analog signal input terminal through said first switching means and having an output; comparator means including a first comparator having a first input terminal connected to said output of the integrator and a second input terminal connected to a first reference voltage source, and a second comparator having a first input terminal connected to said output of said integrator and a second input terminal connected to a second reference voltage source; counter means including a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; clock signal generating means for generating a first clock signal having a first clock frequency and being supplied to said first counter and a second clock signal having a second frequency higher than said first clock frequency and being supplied to said second counter; a plurality of constant current sources connected to said integrator through said second and third switching means, respectively, so that said integrator is supplied with respective constant currents determined according to said first and second predetermined numbers of bits and said first and second clock frequencies of said first and second clock signals, respectively; and control means for controlling said first, second and third switching means and said counter means in response to said clock signal generating means and said comparator means.
Claim 7
Dependent Claim
21 words
An analog-to-digital converter according to claim 1, wherein said first and second predetermined numbers of bits are equal to each other.
Claim 8
Dependent Claim
179 words
A converter for converting an input signal of a first type to a corresponding output signal of a second type, said converter comprising: signal input terminal means receiving said input signal of the first type; an integrator operative in accordance with said input signal; a plurality of constant current sources connected to said integrator so that said integrator is supplied with respective constant currents; counter means including a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and clock signal generating means for generating a first clock signal having a first clock frequency and being supplied to said first counter and a second clock signal having a second clock frequency higher than said first clock frequency and being supplied to said second counter; said plurality of constant current sources having respective currents which are determined according to said first and second predetermined numbers of bits and said first and second clock frequencies of said first and second clock signals, respectively.
Claim 9
Dependent Claim
179 words
A converter for converting an input signal of a first type to a corresponding output signal of a second type, said converter comprising: signal input terminal means receiving said input signal of the first type; an integrator operative in accordance with said input signal; a plurality of constant current sources connected to said integrator so that said integrator is supplied with respective constant currents; counter means including a first counter having a first predetermined number of bits for higher significant bits and a second counter having a second predetermined number of bits for lower significant bits; and clock signal generating means for generating a first clock signal having a first clock frequency and being supplied to said first counter and a second clock signal having a second clock frequency higher than said first clock frequency and being supplied to said second counter; said plurality of constant current sources having respective currents which are determined according to said first and second predetermined numbers of bits and said first and second clock frequencies of said first and second clock signals, respectively.
Claim 10
Dependent Claim
39 words
A converter according to claim 6, wherein said clock signal generating means comprises a master clock generating means for generating said first clock signal and frequency doubler means for generating said second clock signal from said first clock signal.
Claim 11
Dependent Claim
20 words
A converter according to claim 7, wherein said first and second predetermined numbers of bits are equal to each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-15 | 1991-09-14 | 1992-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-15 | 1995-09-14 | 1996-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-15 | 1999-09-14 | 2000-03-15 | $7700.00 | Window Closed / Lapsed |