Digital-to-analog converter

Claim 2

A digital to analog converter circuit for converting digital words of n bits into a corresponding analog level, comprising integrating means having an input to which charging current is applied and an output from which said analog level is derived; a plurality of current sources each providing a constant current at a different respective predetermined level; a plurality of switching means each associated with a respective one of said current sources for coupling the same to said integrating means to provide charging current thereto; a plurality of digital counters each corresponding to a respective one of said switching means and holding a predetermined portion of said n bits, the digital counters in the aggregate holding all said n bits, each said counter being coupled to its respective switching means to provide a switching signal when the contents thereof reach a predetermined count; clock generator means providing clocking signals to said digital counters; and means for receiving said n-bit digital words, dividing the same into a plurality of fragments, and loading each such fragment into a respective one of said counters; the circuit being so configured that when said fragments have been loaded into said counters, said counters begin counting said clocking signals and said switching means are closed for supplying said charging current to said integrating means, and when the contents of each of said counters reaches said predetermined count, that counter provides said switching signal to open the associated switching means to cut off the charging current from the respective current source.

Claim 3

A digital to analog converter circuit according to claim 1, wherein the predetermined levels for the respective current sources are related to each other corresponding to the bit significance of the associated fragments of the n-bit words to be loaded into the respective counters.

Claim 4

A digital to analog converter circuit according to claim 1, wherein the predetermined levels for the current sources associated with the counters containing successive fragments of said n-bit word are in a ratio of 2 n-m where m is the number of bits in the most significant fragment.

Claim 5

A digital to analog converter circuit according to claim 1, wherein each said fragment of said n-bit word contains substantially the same number of bits.

Claim 6

A digital to analog converter circuit according to claim 1, wherein each said switching means includes a switch circuit coupled between the respective current source and said integrating means, and latching means providing a latching signal for closing and opening the associated switch circuit and having a set terminal coupled to receive a set signal provided thereto in correspondence to the loading of said counters and a reset terminal coupled to receive a carry signal from the associated digital counter.

Claim 7

A digital to analog converter circuit according to claim 5, wherein at least one of said switching means includes a further latching circuit providing the associated latching signal to the respective switch circuit in synchronism with said clocking signals.

Claim 8

A digital to analog converter circuit according to claim 6, wherein said at least one of said switching means is that associated with the digital counter holding the fragment of said n-bit word having the most significant bits thereof.

Claim 9

An digital to analog converter circuit for converting digital words of n bits into a corresponding analog level, comprising integrating means having an input to which a charging current is applied and an output from which said analog level is derived; a first and a second current source each providing a constant current at a different respective predetermined level; first and second switching means associated with said first and second current sources, respectively, for coupling the same to said integrating means to provide charging current thereto; a first and a second digital counter respectively associated with said first and second switching means, each holding substantially half of said n bits, the digital counters in the aggregate holding all said n bits, each said counter being coupled to its respective switching means to provide a switching signal when the contents thereof reach a predetermined count; clock generator means providing clocking signals to said digital counters; and means for receiving said n-bit digital words, dividing the same into an upper m bits and a lower n-m bits, m being an integer substantially half the value n, loading said upper m bits into said first counter, and loading said lower n-m bits into said second counter; the circuit being so configured that when said upper and lower bits have been loaded into said counters, the latter begin counting said clocking signals and said first and second switching means are closed for supplying said charging current to said integrating means, and when the contents of each of said counters reaches its predetermined count, that counter provides said switching signal to open the associated switching means to cut off the charging current from the respective current source.

Claim 10

An digital to analog converter circuit for converting digital words of n bits into a corresponding analog level, comprising integrating means having an input to which a charging current is applied and an output from which said analog level is derived; a first and a second current source each providing a constant current at a different respective predetermined level; first and second switching means associated with said first and second current sources, respectively, for coupling the same to said integrating means to provide charging current thereto; a first and a second digital counter respectively associated with said first and second switching means, each holding substantially half of said n bits, the digital counters in the aggregate holding all said n bits, each said counter being coupled to its respective switching means to provide a switching signal when the contents thereof reach a predetermined count; clock generator means providing clocking signals to said digital counters; and means for receiving said n-bit digital words, dividing the same into an upper m bits and a lower n-m bits, m being an integer substantially half the value n, loading said upper m bits into said first counter, and loading said lower n-m bits into said second counter; the circuit being so configured that when said upper and lower bits have been loaded into said counters, the latter begin counting said clocking signals and said first and second switching means are closed for supplying said charging current to said integrating means, and when the contents of each of said counters reaches its predetermined count, that counter provides said switching signal to open the associated switching means to cut off the charging current from the respective current source.

Claim 11

A digital to analog converter circuit according to claim 8, wherein the predetermined levels for said first and second current sources are provided in the ratio of substantially 2 m .

Claim 12

A digital to analog converter circuit according to claim 8, wherein each said switching means includes a switch circuit coupled between the respective current source and said integrating means, and latching means providing a latching signal for closing the associated switch circuit and having a set terminal coupled to receive a set signal provided thereto in correspondence to the loading of said counters and a reset terminal coupled to receive a carry signal from the associated digital counter.

Claim 13

A digital to analog converter circuit according to claim 10, wherein said first switching means further includes a further latching circuit between the associated first-mentioned latching circuit and the associated switch circuit to provide said latching signal thereto in synchronism with said clocking signals.

Claim 14

A digital to analog converter circuit according to claim 8, wherein said means for receiving said n-bit digital words includes first and second shift registers arranged in tandem with the digital words being applied to an input of said second shift register, and an overflow of said second shift register being coupled to an input of said first register, such that said first register holds said m upper bits and said second shift register holds said n-m lower bits.

Claim 15

A digital to analog converter circuit according to claim 12, wherein said means for receiving said n-bit digital words further includes first and second latch means coupled between the respective shift registers and the first and second digital counters.

Claim 16

A digital to analog converter circuit according to claim 13, further comprising timing control circuitry providing a start signal, when each said n-bit word has been entered into the first and second shift registers, to latch the first and second latch means and also to close said first and second switch means.