Coaxial shielded helical delay line and process

Claim 1

A method of forming a shielded delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of: providing a first conductive planar layer as a first of said plurality of superimposed parallel planar layers; forming a pair of conductive strips in a next one of said superimposed parallel planar layers disposed on said first conductive layer; placing dielectric material between said conductive strips; forming a plurality of conductive strips in a plurality of successive ones of said plurality of superimposed parallel planar layers over said next one of said superimposed parallel planar layers; placing dielectric material between the conductive strips in each of said plurality of successive ones of said plurality of superimposed parallel planar layers; forming a pair of conductive strips in an additional one of said superimposed parallel planar layers on said plurality of successive planar layers; depositing dielectric material between said conductive strips of the additional one of said superimposed parallel planar layers; and forming a second conductive planar layer over said additional one of said superimposed parallel planar layers, selected ones of said plurality of conductive strips formed in the plurality of superimposed parallel planar layers being at least partially overlapping and electrically connected and arranged to form a coil having a plurality of turns disposed about and extending along an axis parallel to said plane of said planar substrate, said first and second conductive planar layers, said pairs of conductive strips and others of said plurality of conductive strips being at least partially overlapping and electrically connected and arranged to form a conductive shield spaced from said coil and extending along the length thereof.

Claim 2

A method of forming a shielded delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of: providing a first conductive planar layer as a first of said plurality of superimposed parallel planar layers; forming a pair of conductive strips in a next one of said superimposed parallel planar layers disposed on said first conductive layer; placing dielectric material between said conductive strips; forming a plurality of conductive strips in a plurality of successive ones of said plurality of superimposed parallel planar layers over said next one of said superimposed parallel planar layers; placing dielectric material between the conductive strips in each of said plurality of successive ones of said plurality of superimposed parallel planar layers; forming a pair of conductive strips in an additional one of said superimposed parallel planar layers on said plurality of successive planar layers; depositing dielectric material between said conductive strips of the additional one of said superimposed parallel planar layers; and forming a second conductive planar layer over said additional one of said superimposed parallel planar layers, selected ones of said plurality of conductive strips formed in the plurality of superimposed parallel planar layers being at least partially overlapping and electrically connected and arranged to form a coil having a plurality of turns disposed about and extending along an axis parallel to said plane of said planar substrate, said first and second conductive planar layers, said pairs of conductive strips and others of said plurality of conductive strips being at least partially overlapping and electrically connected and arranged to form a conductive shield spaced from said coil and extending along the length thereof.

Claim 5

A method of forming a delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of: forming and electrically connecting a plurality of conductive strips arranged in said plurality of planar layers to form a coil having a plurality of turns disposed about an axis parallel to said plane; placing a dielectric between said turns and embedding said coil; and forming and arranging additional conductive strips in said plurality of planar layers to provide a conductive shield spaced from, extending along the axis of and substantially enclosing said coil.

Claim 6

A method of forming a delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of: forming and electrically connecting a plurality of conductive strips arranged in said plurality of planar layers to form a coil having a plurality of turns disposed about an axis parallel to said plane; placing a dielectric between said turns and embedding said coil; and forming and arranging additional conductive strips in said plurality of planar layers to provide a conductive shield spaced from, extending along the axis of and substantially enclosing said coil.

Claim 7

A method of forming a delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of: forming a plurality of conductive strips in a first of said plurality of superimposed parallel planar layers; forming additional conductive strips in a plurality of additional ones of said plurality of superimposed parallel planar layers, said conductive strips being formed and arranged in at least a partially superimposed and electrically connected manner to form a coil having a plurality of turns disposed about an axis parallel to said plane; and forming additional conductive strips in said plurality of superimposed parallel planar layers, said additional conductive strips being arranged to provide a conductive shield spaced from, substantially enclosing and coextensive with said coil.

Claim 8

A method of forming a delay line embedded in a planar substrate formed of a plurality of superimposed parallel planar layers, said substrate having a major surface thereof lying in a plane parallel to said planar layers, comprising the steps of: forming a plurality of conductive strips in a first of said plurality of superimposed parallel planar layers; forming additional conductive strips in a plurality of additional ones of said plurality of superimposed parallel planar layers, said conductive strips being formed and arranged in at least a partially superimposed and electrically connected manner to form a coil having a plurality of turns disposed about an axis parallel to said plane; and forming additional conductive strips in said plurality of superimposed parallel planar layers, said additional conductive strips being arranged to provide a conductive shield spaced from, substantially enclosing and coextensive with said coil.