Data processing system with improved output function

Claim 2

An output circuit comprising a first field effect transistor coupled between a first voltage terminal and an output terminal, a second field effect transistor coupled between said output terminal and a second voltage terminal, a third field effect transistor coupled between said output terminal and said first voltage terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, first control means coupled to said first and second terminals for generating a detection signal at its output when at least one of said first and second control signals is present, second control means coupled to said third terminal and the output of said first means for generating a gated signal in accordance with said data signal when said detection signal is not present, means coupled to said second transistor and said second control means for controlling said second transistor in response to said gated signal, third control means coupled to said first transistor and receiving said gated signal and said detection signal for controlling said first transistor in accordance with said gated signal when said detection signal is not present, and fourth control means coupled to said third transistor and receiving said gated signal and said first control signal for making only said third transistor conducting with said first and second transistors non-conducting when said second control signal is present while said first control signal is not present, wherein said output terminal is set at a high impedance state when said first control signal is present, and set at said predetermined voltage through only said third transistor irrespective of the state of said data signal when said second control signal is present and said first control signal is not present.

Claim 3

The output circuit according to claim 1, in which said second transistor is of a first conductivity type and said first and third transistors are of a second channel conductivity type.

Claim 4

The output circuit according to claim 2, in which said first control means includes a first NOR circuit receiving said first and second control signals.

Claim 5

The output circuit according to claim 3, in which said second control means includes a second NOR circuit receiving said data signal and the inverted signal of the output of said first NOR circuit.

Claim 6

The output circuit according to claim 4, in which said third control means includes a third NOR circuit receiving said gated signal and said inverted signal.

Claim 7

The output circuit according to claim 5, in which said fourth control means includes a fourth NOR circuit receiving said gated signal and said first control signal.

Claim 8

An output circuit comprising a first field effect transistor coupled between a first voltage terminal and an output terminal, a second field effect transistor coupled between said output terminal and a second voltage terminal, a third field effect transistor coupled between said first voltage terminal and said output terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, a first means coupled to said first to third terminals and said first and second transistors for making either one of said first and second transistors conducting and the other of said first and second transistors non-conducting in accordance with said data signal when said first and second signals indicate a normal operation mode, a second means coupled to said first and second terminals, said first and second transistors and said first means for making both of said first and second transistors non-conducting when said first and second control signals indicate a first standby mode, and a third means coupled to said first terminal and said third transistor for selectively making said third transistor conducting only when said first and second control signals indicate a second standby mode, whereby said output terminal is selectively provided with a high output impedance or with a clamped output voltage of a level near that of said first voltage terminal through only said third transistor in accordance with said first and second signals irrespective of the state of said data signal.

Claim 9

An output circuit comprising a first field effect transistor coupled between a first voltage terminal and an output terminal, a second field effect transistor coupled between said output terminal and a second voltage terminal, a third field effect transistor coupled between said first voltage terminal and said output terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, a first means coupled to said first to third terminals and said first and second transistors for making either one of said first and second transistors conducting and the other of said first and second transistors non-conducting in accordance with said data signal when said first and second signals indicate a normal operation mode, a second means coupled to said first and second terminals, said first and second transistors and said first means for making both of said first and second transistors non-conducting when said first and second control signals indicate a first standby mode, and a third means coupled to said first terminal and said third transistor for selectively making said third transistor conducting only when said first and second control signals indicate a second standby mode, whereby said output terminal is selectively provided with a high output impedance or with a clamped output voltage of a level near that of said first voltage terminal through only said third transistor in accordance with said first and second signals irrespective of the state of said data signal.

Claim 10

An output circuit comprising a first field effect transistor of a first conductivity type coupled between a first voltage terminal and an output terminal, a second field effect transistor of a second conductivity type coupled between said output terminal and a second voltage terminal, a third field effect transistor of said first conductivity type coupled between said output terminal and said first voltage terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, first control means coupled to said first and second terminals for generating a detection signal at its output when at least one of said first and second control signals is present, said first control means including a first NOR circuit receiving said first and second control signals, second control means coupled to said third terminal and the output of said first means for generating a gated signal in accordance with said data signal when said detection signal is not present, means coupled to said second transistor and said second control means for controlling said second transistor in response to said gated signal, third control means coupled to said first transistor and receiving said gated signal and said detection signal for controlling said first transistor in accordance with said gated signal when said detection signal is not present, and fourth control means coupled to said third transistor and receiving said gated signal and said first control signal for making only said third transistor conducting with said first and second transistors non-conducting irrespective of said data signal when said second control signal is present, wherein said output terminal is set at a high impedance state when said first control signal is present, and set at said predetermined voltage through only said third transistor when said second control signal is present.

Claim 11

An output circuit comprising a first field effect transistor of a first conductivity type coupled between a first voltage terminal and an output terminal, a second field effect transistor of a second conductivity type coupled between said output terminal and a second voltage terminal, a third field effect transistor of said first conductivity type coupled between said output terminal and said first voltage terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, first control means coupled to said first and second terminals for generating a detection signal at its output when at least one of said first and second control signals is present, said first control means including a first NOR circuit receiving said first and second control signals, second control means coupled to said third terminal and the output of said first means for generating a gated signal in accordance with said data signal when said detection signal is not present, means coupled to said second transistor and said second control means for controlling said second transistor in response to said gated signal, third control means coupled to said first transistor and receiving said gated signal and said detection signal for controlling said first transistor in accordance with said gated signal when said detection signal is not present, and fourth control means coupled to said third transistor and receiving said gated signal and said first control signal for making only said third transistor conducting with said first and second transistors non-conducting irrespective of said data signal when said second control signal is present, wherein said output terminal is set at a high impedance state when said first control signal is present, and set at said predetermined voltage through only said third transistor when said second control signal is present.

Claim 12

The output circuit according to claim 8, in which said second control means includes a second NOR circuit receiving said data signal and the inverted signal of the output of said first NOR circuit.

Claim 13

The output circuit according to claim 8, in which said third control means includes a third NOR circuit receiving said gated signal and said inverted signal.

Claim 14

The output circuit according to claim 8, in which said fourth control means includes a fourth NOR circuit receiving said gated signal and said first control signal.

Claim 15

An output circuit comprising a first transistor of a first conductivity type coupled between a first voltage terminal and an output terminal, a second transistor of a second conductivity type coupled between said output terminal and a second voltage terminal, a third transistor of said first conductivity type coupled between said first voltage terminal and said output terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, a first NOR circuit receiving said first and second control signals, a second NOR circuit receiving said data signal and an an inverted signal of an output of said first NOR circuit, means for connecting an output of said second NOR circuit to a control electrode of said second transistor, a third NOR circuit receiving the inverted signal of the output of said first NOR circuit and the output of said second NOR circuit, means for applying an inverted signal of the output of said third NOR circuit to a control electrode of said first transistor, a fourth NOR circuit receiving said first control signal and the output of said second NOR circuit, and means for applying an inverted signal of the output of said fourth NOR circuit to a control electrode of said third transistor.

Claim 16

An output circuit comprising a first transistor of a first conductivity type coupled between a first voltage terminal and an output terminal, a second transistor of a second conductivity type coupled between said output terminal and a second voltage terminal, a third transistor of said first conductivity type coupled between said first voltage terminal and said output terminal, a conductive resistance of said third transistor being larger than that of said first transistor, a first terminal receiving a first control signal, a second terminal receiving a second control signal independent of said first control signal, a third terminal receiving a data signal, a first NOR circuit receiving said first and second control signals, a second NOR circuit receiving said data signal and an an inverted signal of an output of said first NOR circuit, means for connecting an output of said second NOR circuit to a control electrode of said second transistor, a third NOR circuit receiving the inverted signal of the output of said first NOR circuit and the output of said second NOR circuit, means for applying an inverted signal of the output of said third NOR circuit to a control electrode of said first transistor, a fourth NOR circuit receiving said first control signal and the output of said second NOR circuit, and means for applying an inverted signal of the output of said fourth NOR circuit to a control electrode of said third transistor.

Claim 17

The output circuit according to claim 12, wherein said first conductivity type is P channel and said second conductivity type is N channel.