Patent US4726045A successfully refreshed from Google Patents.
US4726045A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low jitter digital delay generator
Assignee: Micron Technology Inc
•
Filing: 1986-03-28
•
Granted: 1988-02-16
•
Expires: 2006-03-28
Abstract
Abstract A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded including the condition of a lowest order stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.
Inventors
- 👤 George J. Caspell
- 👤 Agoston Agoston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K23/00; H03K23/64; H03K23/66; H03K23/665
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
251 words
Circuitry for accurately timing a predetermined period, comprising: an asynchronous counter comprising a plurality of bistable stages including a first stage that is triggered first, and a last stage that is triggered last, wherein each stage is triggered after the preceding stage, each stage providing an output having a divided relation to its input, decoder means for receiving inputs responsive to conditions of selected bistable stages including said first stage and for decoding the same, including detecting a change in condition of said first stage to a predetermined state for supplying a decoded indication when the remainder of the selected stages have already attained predetermined states, whereby a stable decoded indication is provided in response to said first stage attaining a predetermined state at a time different from the times the remainder of said selected stages attain predetermined states, means responsive to said stable decoded indication for initiating a timing output pulse, second decoder means responsive to conditions of less than all said selected bistable stages including only stages changing state more frequently than the last stage of said selected bistable stages for supplying a second decoded indication after the first mentioned decoded indication, including means for concluding said timing output pulse in response to said second decoded indication, and means for automatically loading said counter substantially at the conclusion of said timing output pulse with a selected number for determining the lapse of time between initial triggering of said first stage and the presence of the first mentioned decoded indication.
Claim 2
Dependent Claim
251 words
Circuitry for accurately timing a predetermined period, comprising: an asynchronous counter comprising a plurality of bistable stages including a first stage that is triggered first, and a last stage that is triggered last, wherein each stage is triggered after the preceding stage, each stage providing an output having a divided relation to its input, decoder means for receiving inputs responsive to conditions of selected bistable stages including said first stage and for decoding the same, including detecting a change in condition of said first stage to a predetermined state for supplying a decoded indication when the remainder of the selected stages have already attained predetermined states, whereby a stable decoded indication is provided in response to said first stage attaining a predetermined state at a time different from the times the remainder of said selected stages attain predetermined states, means responsive to said stable decoded indication for initiating a timing output pulse, second decoder means responsive to conditions of less than all said selected bistable stages including only stages changing state more frequently than the last stage of said selected bistable stages for supplying a second decoded indication after the first mentioned decoded indication, including means for concluding said timing output pulse in response to said second decoded indication, and means for automatically loading said counter substantially at the conclusion of said timing output pulse with a selected number for determining the lapse of time between initial triggering of said first stage and the presence of the first mentioned decoded indication.
Claim 3
Dependent Claim
61 words
The circuitry according to claim 1 wherein each said bistable stage includes a triggering input terminal and an output terminal at which the state of the stage is indicated, wherein the output terminal of each stage except the last is connected in driving relation to the triggering input of the next stage, said decoder means being connected to stage output terminals.
Claim 4
Dependent Claim
14 words
The circuitry according to claim 2 wherein said decoder means comprises an AND gate.
Claim 5
Dependent Claim
230 words
Circuitry for accurately timing a predetermined period, comprising: an asynchronous counter comprising a plurality of bistable stages wherein the first such stage receives a trigger input and the output of such stage triggers the next, each stage providing an output having a divided relation to its input, decoder means for receiving inputs from selected outputs of said bistable stages and detecting said outputs, including detection of the active output of the first stage before activating of the following stage by the output of the first stage, for supplying a decoded indication when all the selected outputs attain a predetermined full count condition, said first stage being the last to attain said active output after the rest of the stages are stable so as to produce a stable decoded indication, means responsive to said stable decoded indication for initiating a timing output pulse, second decoder means responsive to conditions of less than all the selected outputs attaining a predetermined count condition for supplying a second decoded indication after the first mentioned decoded indication, including means for concluding said timing output pulse in response to said second decoded indication, and means for automatically loading said counter substantially at the conclusion of said timing output pulse with a selected number for determining the lapse of time between the first triggering of sid first stage and the presence of the first mentioned decoded indication.
Claim 6
Dependent Claim
230 words
Circuitry for accurately timing a predetermined period, comprising: an asynchronous counter comprising a plurality of bistable stages wherein the first such stage receives a trigger input and the output of such stage triggers the next, each stage providing an output having a divided relation to its input, decoder means for receiving inputs from selected outputs of said bistable stages and detecting said outputs, including detection of the active output of the first stage before activating of the following stage by the output of the first stage, for supplying a decoded indication when all the selected outputs attain a predetermined full count condition, said first stage being the last to attain said active output after the rest of the stages are stable so as to produce a stable decoded indication, means responsive to said stable decoded indication for initiating a timing output pulse, second decoder means responsive to conditions of less than all the selected outputs attaining a predetermined count condition for supplying a second decoded indication after the first mentioned decoded indication, including means for concluding said timing output pulse in response to said second decoded indication, and means for automatically loading said counter substantially at the conclusion of said timing output pulse with a selected number for determining the lapse of time between the first triggering of sid first stage and the presence of the first mentioned decoded indication.
Claim 7
Dependent Claim
56 words
The circuitry according to claim 1 further including triggering means responsive to an input trigger and coupled for enabling the first stage of said counter to count a periodic input clock signal, and wherein said means responsive to said stable decoded indication for initiating a timing output pulse is triggered by said periodic input clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |