Circuit for applying a voltage to a memory cell MOS capacitor of a semiconductor memory device

Claim 1

A semiconductor memory device comprising: a plurality of dynamic memory cells, each of the dynamic memory cells comprising a MOS memory capacitor and a transfer MOS transistor, one terminal of the MOS memory capacitor being connected to one terminal of the source-drain path of the transfer MOS transistor, the other terminal of the source-drain path of the transfer MOS transistor being connected to a bit line, and the gate of the transfer MOS transistor being connected to a word line; and a voltage-applying circuit having an output terminal, the output terminal being connectd to the other terminal of said MOS memory capacitor of each of said plural MOS memory cells, the voltage-applying circuit having means for selectively applying through said output terminal to said other terminal of the MOS memory capacitor of each of the plural MOS memory cells a first voltage for screening the MOS memory capacitors and a second voltage for operating the MOS memory capacitors, the first voltage for screening the MOS memory capacitors being higher than the second voltage for operating the MOS memory capacitors and being sufficient to detect any faulty MOS memory capacitors.