Patent US4725979A successfully refreshed from Google Patents.
US4725979A
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Emitter coupled logic circuit having fuse programmable latch/register bypass
Assignee: Lattice Semiconductor Corp
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Filing: 1986-12-05
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Granted: 1988-02-16
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Expires: 2006-12-05
Abstract
Abstract An emitter coupled logic circuit includes a bypass circuit which provides a conductive path for current when a programmable fuse is blown, so that input data is transmitted independently of the state of a clock signal. In one implementation, the circuit takes a register configuration having a master section and a slave section, each incorporating a programmable fuse. When the fuse in just one section is intact, the circuit serves as a clocked latch. When both fuses are blown, the bypass circuit is enabled so that the register functions as a combinatorial circuit which produces an output signal dependent on the input signal without reference to a clock signal.
Inventors
- 👤 Barry A. Hoberman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:48
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1084; G11C17/00; G11C17/14; G11C17/18; G11C7/1006; G11C7/1051; G11C7/1057; G11C7/106; G11C7/1087; G11C7/1093; H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
206 words
A programmable logic circuit for storing data comprising: a first transistor and a second transistor, each having emitter base and collector electrodes, the emitters of said first and second transistors being connected in a common emitter circuit; a first current source for applying current to the common emitter circuit of said first and second transistors; means for applying a clock signal to the base of said first transistor; means for applying a first reference voltage to the base of said second transistor; a third transistor and a fourth transistor, each having emitter, base and collector electrodes, the emitters of said third and fourth transistors being connected; means for applying a data input signal to the base of said third transistor; means for applying a second reference voltage to the base of said fourth transistor; a bypass circuit coupled at one end to a junction between said current source and the common emitter circuit of said first and second transistors and coupled at the other end to the common emitter circuit of said third and fourth transistors; a programmable circuit including a fuse coupled to said bypass circuit, so that the state of the fuse determines whether the function of the logic circuit is combinatorial or latched.
Claim 2
Dependent Claim
206 words
A programmable logic circuit for storing data comprising: a first transistor and a second transistor, each having emitter base and collector electrodes, the emitters of said first and second transistors being connected in a common emitter circuit; a first current source for applying current to the common emitter circuit of said first and second transistors; means for applying a clock signal to the base of said first transistor; means for applying a first reference voltage to the base of said second transistor; a third transistor and a fourth transistor, each having emitter, base and collector electrodes, the emitters of said third and fourth transistors being connected; means for applying a data input signal to the base of said third transistor; means for applying a second reference voltage to the base of said fourth transistor; a bypass circuit coupled at one end to a junction between said current source and the common emitter circuit of said first and second transistors and coupled at the other end to the common emitter circuit of said third and fourth transistors; a programmable circuit including a fuse coupled to said bypass circuit, so that the state of the fuse determines whether the function of the logic circuit is combinatorial or latched.
Claim 3
Dependent Claim
49 words
A programmable logic circuit as in claim 1, wherein said bypass circuit comprises a transistor having its emitter coupled to said current source and having its collector coupled to the common emitter circuit of said third and fourth transistors, and having its base connected to a reference voltage source.
Claim 4
Dependent Claim
30 words
A programmable logic circuit as in claim 1, including means for blowing said fuse, said fuse blowing means comprising programmable decode means and serially connected transistors coupled to said fuse.
Claim 5
Dependent Claim
18 words
A programmable logic circuit as in claim 3, wherein said decode means comprises a plurality of Schottky diodes.
Claim 6
Dependent Claim
15 words
A programmable logic circuit as in claim 1, including biasing diodes coupled to said fuse.
Claim 7
Dependent Claim
109 words
A programmable logic circuit as in claim 1, including second and third current sources; a fifth transistor and a sixth transistor having respectively base and collector electrodes and emitters, said emitters of said fifth and sixth transistors being coupled to said second and third current sources respectively, and the base of said fifth and sixth transistors being coupled to the collector circuits of said third and fourth transistors respectively; seventh and eighth transistors having respectively base and collector electrodes and coupled emitters that are connected to the collectors of said first and second transistors, and having their bases connected to the emitters of said fifth and sixth transistors respectively.
Claim 8
Dependent Claim
78 words
A programmable logic circuit as in claim 6, comprising master and slave circuit sections, each of said sections separately including the elements of claim 6, wherein the junction between the third current source and the emitter of said sixth transistor of said master section is tied to the base electrode of the third transistor of said slave section, each section including an independent programmable fuse and a decode circuit coupled to said fuse for selectively blowing said fuse.
References Cited (Backward Citations)
US4099070A
Cited
US4464735A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |