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Patent US4723258A successfully refreshed from Google Patents.
US4723258A
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Counter circuit
Assignee: NEC Electronics Corp
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Filing: 1986-03-18
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Granted: 1988-02-02
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Expires: 2006-03-18
Abstract
Abstract A multi-digit counter circuit performs both successive data production function and non-successive data production. Successive data is produced by an increment or decrement operation according to a first carry (borrow) signal. Non-successive data is produced by a control circuit which applies a second carry (borrow) signal independently of the first carry (borrow) signal to an arbitrary selected digit or digits. The arbitrary digit is designated according to the distance between the preceding data and the following data to be produced.
Inventors
- 👤 Hideo Tanaka
- 👤 Ichiro Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/321; G06F9/34
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
183 words
A counter circuit, comprising; counter means including a plurality of ordered stages, each of said stages except for a highest ordered stage including a carry signal input end and a carry signal output end, and said highest ordered stage including a carry signal input end; a plurality of first switching means, each being coupled between said carry signal output end of a lower ordered stage and said carry signal input end of a following higher ordered stage for transferring a carry signal from said lower ordered stage to said higher ordered stage when actuated; means for generating a control signal; a plurality of second switching means, each being coupled between a carry signal input end of each stage and said control signal generating means for transferring said control signal to the associated stage when actuated; and means for actuating one or ones of said plurality of said second switching means so as to couple said control signal to a selected stage or stages, and for actuating those of said first switching means associated with carry signal input ends of the remaining, non-selected stages.
Claim 2
Dependent Claim
183 words
A counter circuit, comprising; counter means including a plurality of ordered stages, each of said stages except for a highest ordered stage including a carry signal input end and a carry signal output end, and said highest ordered stage including a carry signal input end; a plurality of first switching means, each being coupled between said carry signal output end of a lower ordered stage and said carry signal input end of a following higher ordered stage for transferring a carry signal from said lower ordered stage to said higher ordered stage when actuated; means for generating a control signal; a plurality of second switching means, each being coupled between a carry signal input end of each stage and said control signal generating means for transferring said control signal to the associated stage when actuated; and means for actuating one or ones of said plurality of said second switching means so as to couple said control signal to a selected stage or stages, and for actuating those of said first switching means associated with carry signal input ends of the remaining, non-selected stages.
Claim 3
Dependent Claim
31 words
The circuit of claim 1, wherein those ones of the first and second switching means coupled to the carry signal input end of the same stage are complementarily actuated and deactuated.
Claim 4
Dependent Claim
63 words
A circuit as claimed in claim 1, in which said actuating means comprises register means for storing information designating at least one stage, and decoder means for decoding the information stored in said register means to output first actuating signal means for actuating that one of said second switching means which is connected to the carry signal input end of each designated stage.
Claim 5
Dependent Claim
37 words
A circuit as claimed in claim 3, wherein said decoder means further generates one or more second deactuating signals for deactuating those of said second switching means connected to the carry signal input ends of non-designated stages.
Claim 6
Dependent Claim
66 words
A circuit as claimed in claim 4, wherein said actuating means further includes means for deactuating the first switching means connected to the carry signal input end of each said designated stage in response to said first actuating signal means and for actuating the first switching means connected to the carry signal input end of each said non-designated stage in response to said second deactuating signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-01 | 1991-08-03 | 1992-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-01 | 1995-08-03 | 1996-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-01 | 1999-08-03 | 2000-02-02 | $7700.00 | Window Closed / Lapsed |