US4723246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated scrambler-encoder using PN sequence generator
Assignee: Tandem Computers Inc
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Filing: 1985-07-25
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Granted: 1988-02-02
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Expires: 2005-07-25
Abstract
Abstract Simplified method and apparatus for performing integrated scrambling and encoding or descrambling and decoding of block code digital transmissions is disclosed. The method involves setting the scrambling length equal to an integer multiple of the block length, and then implementing a pseudorandom number sequence generator within the block length counter. The output of the pseudorandom number sequence generator is then logically combined with the incoming data to provide scrambled data, simplifying the complexity of the encoder or decoder significantly.
Inventors
- 👤 Edward J. Weldon, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:54
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03866
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
122 words
A scrambler suitable for use in a digital transmission communications system for transmitting blocks of data of preselected lengths having: counter means including an input and a plurality of stages operatively connected for counting blocks of data of said preselected lengths, exclusive-or means connected to receive the output of at least one of the stages and to provide feedback through said input to the counter means for causing the counter means to generate pseudorandom number of sequences, the counting stages operatively connected outputting the block length of the scrambled data as an integer multiple of the pseudorandom number sequence; and, output means for combining said input means and the pseudorandom number sequence of the counter means for supplying a scrambled output signal.
Claim 2
Dependent Claim
122 words
A scrambler suitable for use in a digital transmission communications system for transmitting blocks of data of preselected lengths having: counter means including an input and a plurality of stages operatively connected for counting blocks of data of said preselected lengths, exclusive-or means connected to receive the output of at least one of the stages and to provide feedback through said input to the counter means for causing the counter means to generate pseudorandom number of sequences, the counting stages operatively connected outputting the block length of the scrambled data as an integer multiple of the pseudorandom number sequence; and, output means for combining said input means and the pseudorandom number sequence of the counter means for supplying a scrambled output signal.
Claim 3
Dependent Claim
145 words
A scrambler for use in a digital transmission system for transmitting blocks of data having a preselected number of digits including input means for receiving data, block code scrambling means having an input and including a plurality of stages operatively connected for counting block code lengths having a preselected number of digits, scrambling means interconnected between at least one of the stages of the block code scrambling means and the input to the block code scrambling means for causing the operatively connected stages to generate pseudorandom number sequences, the counting stages as operatively connected outputting the block code length of the transmitted data as an integer multiple of the pseudorandom number sequences of the scrambling means; and output means for supplying a scrambled version of the data received by the input means combining the input means for receiving data and the block code scrambling means.
Claim 4
Dependent Claim
145 words
A scrambler for use in a digital transmission system for transmitting blocks of data having a preselected number of digits including input means for receiving data, block code scrambling means having an input and including a plurality of stages operatively connected for counting block code lengths having a preselected number of digits, scrambling means interconnected between at least one of the stages of the block code scrambling means and the input to the block code scrambling means for causing the operatively connected stages to generate pseudorandom number sequences, the counting stages as operatively connected outputting the block code length of the transmitted data as an integer multiple of the pseudorandom number sequences of the scrambling means; and output means for supplying a scrambled version of the data received by the input means combining the input means for receiving data and the block code scrambling means.
Claim 5
Dependent Claim
199 words
A scrambler for use in a digital transmission system for transmitting blocks of data of preselected lengths including: input means for receiving incoming data; clock means for generating clock signals; a counter having a clock input to generate counting, first and second counting outputs, and a scrambling output comprising a connection to at least one of the stages of said counter, the counting stages operatively connected outputting the block length of the combined group of data and parity bits being an integer multiple of a pseudorandom number sequence used to scramble the data; parity check generator means connected to said input means for receiving data for generating and storing parity data responsive to said passing data stream; switching logic means including a first output means responsive to the first output of said counter for gating data and second output means responsive to the second output of said counter for gating stored parity data from said parity check generator means; logic combination means including an exclusive OR gate for sequentially receiving data and parity bits on one input and the output of the pseudorandom number sequence of said counter on the other input to scramble sequentially data and parity bits.
Claim 6
Dependent Claim
199 words
A scrambler for use in a digital transmission system for transmitting blocks of data of preselected lengths including: input means for receiving incoming data; clock means for generating clock signals; a counter having a clock input to generate counting, first and second counting outputs, and a scrambling output comprising a connection to at least one of the stages of said counter, the counting stages operatively connected outputting the block length of the combined group of data and parity bits being an integer multiple of a pseudorandom number sequence used to scramble the data; parity check generator means connected to said input means for receiving data for generating and storing parity data responsive to said passing data stream; switching logic means including a first output means responsive to the first output of said counter for gating data and second output means responsive to the second output of said counter for gating stored parity data from said parity check generator means; logic combination means including an exclusive OR gate for sequentially receiving data and parity bits on one input and the output of the pseudorandom number sequence of said counter on the other input to scramble sequentially data and parity bits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-01 | 1991-08-03 | 1992-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-01 | 1995-08-03 | 1996-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-01 | 1999-08-03 | 2000-02-02 | $7700.00 | Window Closed / Lapsed |