US4133974A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for locally enciphering prime data
Assignee: Datotek Inc
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Filing: 1976-11-05
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Granted: 1979-01-09
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Expires: 1996-11-05
Abstract
Abstract The specification discloses circuitry useful in a digital cryptographic system having a digital prime sequence which controls the generation of randomized key data. The circuitry includes a register for storing the digital prime sequence prior to generation of the randomized key data. A memory is provided which includes address inputs and data outputs and which stores predetermined digital relationships. A stage of the register is connected to an address input of the memory to select one of the stored digital relationships. A source of selectable digital bits is connected to another address input of the memory. The data outputs of the memory are operable to be coupled to the input of the register for generating an enciphered digital prime sequence. A clock clocks the contents of the register through the stages of the register in order to cause the enciphered digital prime sequence to be loaded into the register. The enciphered prime sequence is then utilized to control the generation of randomized data for use in the cryptographic system.
Inventors
- 👤 Barrie O. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:09
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; H04L9/0668; H04L2209/00; H04L2209/12
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
114 words
In a digital cryptographic system having a digital prime sequence for controlling the generation of randomized key data at a local station and at a remote station, the combination comprising: means for transmitting the digital prime sequence from the local station to the remote station, multistage means for storing the digital prime sequence at the local station prior to generation of the randomized key data, means responsive to a portion of said stored prime sequence for enciphering said stored prime sequence, means for replacing the contents of said multistage means with said enciphered prime sequence, and means for applying the contents of said multistage means to control the generation of the randomized key data.
Claim 2
Dependent Claim
114 words
In a digital cryptographic system having a digital prime sequence for controlling the generation of randomized key data at a local station and at a remote station, the combination comprising: means for transmitting the digital prime sequence from the local station to the remote station, multistage means for storing the digital prime sequence at the local station prior to generation of the randomized key data, means responsive to a portion of said stored prime sequence for enciphering said stored prime sequence, means for replacing the contents of said multistage means with said enciphered prime sequence, and means for applying the contents of said multistage means to control the generation of the randomized key data.
Claim 3
Dependent Claim
36 words
The improvement of claim 1 and further comprising: storage means for controlling the encipherment of said prime sequence according to a stored non-linear numeric relationship addressed in response to said portion of said stored prime sequence.
Claim 4
Dependent Claim
14 words
The improvement of claim 2 wherein said storage means comprises a read only memory.
Claim 5
Dependent Claim
24 words
The improvement of claim 3 wherein at least one of the addresses of said memory is controlled by a portion of said prime sequence.
Claim 6
Dependent Claim
24 words
The improvement of claim 3 wherein at least one of the addresses of said memory is controlled by a selectable source of digital signals.
Claim 7
Dependent Claim
147 words
In a digital cryptographic system having a digital prime sequence for controlling the generation of randomized key data, the combination comprising: register means for storing the digital prime sequence prior to generation of the randomized key data, memory means having address inputs and data outputs and storing predetermined digital relationships, a stage of said register means being connected to an address input of said memory means for selecting ones of said stored digital relationships. a source of selectable digital bits connected to another address input of said memory means, said data outputs of said memory means operable to be coupled to the input of said register means for generating an enciphered digital prime sequence, and means for clocking the contents of said register means through the stages of said register means in order to cause said enciphered digital prime sequence to be loaded into said register means.
Claim 8
Dependent Claim
147 words
In a digital cryptographic system having a digital prime sequence for controlling the generation of randomized key data, the combination comprising: register means for storing the digital prime sequence prior to generation of the randomized key data, memory means having address inputs and data outputs and storing predetermined digital relationships, a stage of said register means being connected to an address input of said memory means for selecting ones of said stored digital relationships. a source of selectable digital bits connected to another address input of said memory means, said data outputs of said memory means operable to be coupled to the input of said register means for generating an enciphered digital prime sequence, and means for clocking the contents of said register means through the stages of said register means in order to cause said enciphered digital prime sequence to be loaded into said register means.
Claim 9
Dependent Claim
25 words
The combination of claim 6 wherein said register means has the same number of stages as the number of digital bits within said prime sequence.
Claim 10
Dependent Claim
27 words
The combination of claim 6 wherein a stage of said register means is modulo-2 added to a signal representative of said data outputs of said memory means.
Claim 11
Dependent Claim
15 words
The combination of claim 6 wherein said data outputs are modulo-2 added to one another.
Claim 12
Dependent Claim
29 words
The combination of claim 6 and further comprising: means for selectively connecting the input of said register means to receive either said prime sequence or said enciphered prime sequence.
Claim 13
Dependent Claim
26 words
The combination of claim 6 wherein said source of selectable digital bits comprises a manually operable set of switches for generating a sequence of digital signals.
Claim 14
Dependent Claim
14 words
The combination of claim 6 wherein said memory means comprises a read only memory.
Claim 15
Dependent Claim
16 words
The combination of claim 6 wherein said stored predetermined digital relationships are non-linear to one another.
Claim 16
Dependent Claim
115 words
In a ditigal cryptographic system having a digital prime sequence for controlling the generation of randomized key data, the combination comprising: multistage means for storing the digital prime sequence prior to generation of the randomized key data, memory means having address inputs and data outputs and storing predetermined digital relationships, a stage of said multistage means being connected to an address input of said memory means for selecting ones of said stored digital relationships, said data outputs of said memory means operable to be coupled to the input of said multistage means for generating an enciphered digital prime sequence, and means for replacing the contents of said multistage means with said enciphered digital prime sequence.
Claim 17
Dependent Claim
115 words
In a ditigal cryptographic system having a digital prime sequence for controlling the generation of randomized key data, the combination comprising: multistage means for storing the digital prime sequence prior to generation of the randomized key data, memory means having address inputs and data outputs and storing predetermined digital relationships, a stage of said multistage means being connected to an address input of said memory means for selecting ones of said stored digital relationships, said data outputs of said memory means operable to be coupled to the input of said multistage means for generating an enciphered digital prime sequence, and means for replacing the contents of said multistage means with said enciphered digital prime sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-01-08 | 1982-07-10 | 1983-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-01-08 | 1986-07-10 | 1987-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-01-08 | 1990-07-10 | 1991-01-09 | $7700.00 | Window Closed / Lapsed |