US3781473A
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Random digital code generator
Assignee: Datotek Inc
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Filing: 1971-04-15
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Granted: 1973-12-25
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Expires: 1991-04-15
Abstract
Abstract The specification discloses a random code generator for generating a randomized digital key stream. A plurality of shift registers are each operable to generate a randomized digital signal, the cycle period of each of the shift registers being prime to one another. Nonlinear combining circuitry receives and combines the digital signals generated by the shift registers for production of a randomized digital key stream. Mode control circuitry is responsive to the key stream for randomly varying the interconnection and mode of operation of the shift registers between a plurality of different modes. Circuitry is also responsive to the key stream for randomly varying the number of steps taken by the shift registers during the various modes of operation. The shift registers are operable during a priming mode to generate a random prime signal for synchronization of encoding and decoding ciphering devices. If desired, a read only memory may be connected into the generator to further randomize the digital key stream.
Inventors
- 👤 G Goode
- 👤 K Branscome
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:13
CPC Classifications
H; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; H04L9/0668
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
129 words
A code generator having different modes of operation for generating a random key stream comprising: a plurality of autonomous sequential circuits each automatically operable during the generation of said random key stream in one mode of operation to generate generally randomized digital signals, the cycle period of each of said circuits being relatively prime to the cycle periods of the other circuits, means for automatically connecting at least two of said sequential circuits as a maximal length shift register generator for generation of long series of randomized digital signals in a second mode of operation during generation of said random key stream, and nonlinear combining circuitry for receiving and combining said digital signals in either of said two modes of operation for generation of a randomized digital key stream
Claim 2
Dependent Claim
129 words
A code generator having different modes of operation for generating a random key stream comprising: a plurality of autonomous sequential circuits each automatically operable during the generation of said random key stream in one mode of operation to generate generally randomized digital signals, the cycle period of each of said circuits being relatively prime to the cycle periods of the other circuits, means for automatically connecting at least two of said sequential circuits as a maximal length shift register generator for generation of long series of randomized digital signals in a second mode of operation during generation of said random key stream, and nonlinear combining circuitry for receiving and combining said digital signals in either of said two modes of operation for generation of a randomized digital key stream
Claim 3
Dependent Claim
19 words
The code generator of claim 1 wherein said sequential circuits comprise shift registers, each having a different cycle period.
Claim 4
Dependent Claim
30 words
The code generator of claim 1 and further comprising: means operable during generation of said key stream for randomly varying the interconnection and mode of operation of said sequential circuits.
Claim 5
Dependent Claim
39 words
The code generator of claim 1 and further comprising: a read only memory operable to generate an electrical signal for combination with said key stream generated by said nonlinear combining circuitry to provide a more randomized digital key stream.
Claim 6
Dependent Claim
26 words
The code generator of claim 1 wherein said sequential circuits comprise a plurality of shift registers and a register containing a stored code for the day.
Claim 7
Dependent Claim
22 words
The code generator of claim 5 and further comprising thumbwheel switch means for loading said code for the day into said register.
Claim 8
Dependent Claim
78 words
A random code generator for generating a stream of randomized digital signals comprising: a plurality of autonomous sequential circuits, means for interconnecting said sequential circuits in a plurality of different configurations during the generating of said stream of randomized digital signals, each configuration operable to generate randomized digital signals, and means automatically operable during the generation of said stream for controlling said interconnecting means in a manner in order to randomly vary the interconnection of said sequential circuits.
Claim 9
Dependent Claim
78 words
A random code generator for generating a stream of randomized digital signals comprising: a plurality of autonomous sequential circuits, means for interconnecting said sequential circuits in a plurality of different configurations during the generating of said stream of randomized digital signals, each configuration operable to generate randomized digital signals, and means automatically operable during the generation of said stream for controlling said interconnecting means in a manner in order to randomly vary the interconnection of said sequential circuits.
Claim 10
Dependent Claim
23 words
The random code generator of claim 7 wherein in each said configuration, said sequential circuits have cycles which are prime to one another.
Claim 11
Dependent Claim
21 words
The random code generator of claim 7 wherein said sequential circuits comprise registers operable to be connected as shift register generators.
Claim 12
Dependent Claim
21 words
The random code generator of claim 7 wherein said sequential circuits comprise registers operable to be connected in a circulating mode.
Claim 13
Dependent Claim
53 words
A random code generator comprising: a plurality of autonomous sequential circuits each operable to generate randomized digital signals, and means operable in response to selected portions of said randomized digital signals for randomly controlling the number of sequential steps taken by said autonomous sequential circuits between the generation of subsequent succesSive digital signals.
Claim 14
Dependent Claim
53 words
A random code generator comprising: a plurality of autonomous sequential circuits each operable to generate randomized digital signals, and means operable in response to selected portions of said randomized digital signals for randomly controlling the number of sequential steps taken by said autonomous sequential circuits between the generation of subsequent succesSive digital signals.
Claim 15
Dependent Claim
22 words
The random code generator of claim 11 wherein said sequential circuits comprise shift registers operable to be connected as shift register generators.
Claim 16
Dependent Claim
20 words
The random code generator of claim 11 wherein said means comprises a binary counter operated by a random digital signal.
Claim 17
Dependent Claim
73 words
In a random code generator, an automatic system for generating secure random prime data for use as an initial starting state to synchronize a remote terminal comprising: a cyclically operable sequential stepping circuit operable to automatically generate digital bits during an idle mode, means for terminating generation of said stepping circuit, and means for automatically generating secure prime data which corresponds to digital bits stored in said stepping circuit after termination of generation.
Claim 18
Dependent Claim
73 words
In a random code generator, an automatic system for generating secure random prime data for use as an initial starting state to synchronize a remote terminal comprising: a cyclically operable sequential stepping circuit operable to automatically generate digital bits during an idle mode, means for terminating generation of said stepping circuit, and means for automatically generating secure prime data which corresponds to digital bits stored in said stepping circuit after termination of generation.
Claim 19
Dependent Claim
25 words
The random prime generation system of claim 14 wherein said stepping circuit comprises a plurality of shift registers connected together as a shift register generator.
Claim 20
Dependent Claim
37 words
The random prime generation system of claim 15 wherein a predetermined number of digital bits are fed from the output of one of said registers to the input of another of said registers to provide prime data.
Claim 21
Dependent Claim
116 words
A random code generator for use with a digital cryptographic system comprising: a plurality of autonomous sequential circuits each operable to generate a randomized linear digital signal, the cycle periods of each of said sequential circuits being prime to one another, nonlinear combining circuitry for receiving and combining said linear digital signals to generate a randomized digital key stream, means responsive to said digital key stream for randomly varying the interconnections and mode of operation of said sequential circuits, means for randomly varying the number of steps taken by said sequential circuits between successive signal generations, and means for operating said sequential circuits to generate a random prime signal prior to generation of said key stream.
Claim 22
Dependent Claim
116 words
A random code generator for use with a digital cryptographic system comprising: a plurality of autonomous sequential circuits each operable to generate a randomized linear digital signal, the cycle periods of each of said sequential circuits being prime to one another, nonlinear combining circuitry for receiving and combining said linear digital signals to generate a randomized digital key stream, means responsive to said digital key stream for randomly varying the interconnections and mode of operation of said sequential circuits, means for randomly varying the number of steps taken by said sequential circuits between successive signal generations, and means for operating said sequential circuits to generate a random prime signal prior to generation of said key stream.
Claim 23
Dependent Claim
26 words
The random code generator of claim 17 wherein said sequential circuits comprise shift registers operable to be connected in series and as individual shift register generators.
Claim 24
Dependent Claim
25 words
The random code generator of claim 17 and further comprising: read only memory means for generating a signal for combination by said nonlinear combining circuitry.
Claim 25
Dependent Claim
24 words
The random code generator of claim 17 and further comprising means for preventing said sequential circuits from being hung up with identical digital bits.
Claim 26
Independent Claim
60 words
A method of ciphering data comprising: generating a plurality of linearly ciphered digital signals with sequential stepping circuits having cycles relatively prime to one another, nonlinearly combining said linearly ciphered digital signals into a single random digital key stream, and randomly varying the mode of operation and interconnections of the sequential stepping circuits during the generation of said key stream.
Claim 27
Independent Claim
60 words
A method of ciphering data comprising: generating a plurality of linearly ciphered digital signals with sequential stepping circuits having cycles relatively prime to one another, nonlinearly combining said linearly ciphered digital signals into a single random digital key stream, and randomly varying the mode of operation and interconnections of the sequential stepping circuits during the generation of said key stream.
Claim 28
Dependent Claim
20 words
The method of claim 21 and further comprising: randomly varying the number of steps taken by the sequential stepping circuits.
Claim 29
Independent Claim
54 words
The method of generating random digital signals comprising: stepping a plurality of autonomous sequential circuits to generate a plurality of random digital signals, nonlinearly combining said random digital signals to generate a random key stream, and randomly varying the number of subsequent steps taken by said circuits in response to said random key stream.
Claim 30
Independent Claim
54 words
The method of generating random digital signals comprising: stepping a plurality of autonomous sequential circuits to generate a plurality of random digital signals, nonlinearly combining said random digital signals to generate a random key stream, and randomly varying the number of subsequent steps taken by said circuits in response to said random key stream.
Claim 31
Independent Claim
77 words
A method of automatically generating random prime data for use as an initial starting state to synchronize a remote digital cipering system comprising: automatically generating randomized digital bits from a plurality of interconnected sequential circuits operating in an idle mode, generating an initiate prime signal, and terminating said generation of said randomized digital bits in response to said initiate prime signal and automatically utilizing the digital bits in said sequEntial circuits as prime data for digital ciphering.
Claim 32
Independent Claim
77 words
A method of automatically generating random prime data for use as an initial starting state to synchronize a remote digital cipering system comprising: automatically generating randomized digital bits from a plurality of interconnected sequential circuits operating in an idle mode, generating an initiate prime signal, and terminating said generation of said randomized digital bits in response to said initiate prime signal and automatically utilizing the digital bits in said sequEntial circuits as prime data for digital ciphering.
Claim 33
Dependent Claim
70 words
A random code generator comprising: a plurality of autonomous sequential circuits, means for interconnecting said sequential circuits in a plurality of different configurations, each configuration operable to generate randomized digital signals, means for nonlinearly combining the digital signals generated by said sequential circuits, and means responsive to the output of said combining means for randomly controlling said interconnecting means in order to randomly vary the interconnection of said sequential circuits.
Claim 34
Dependent Claim
70 words
A random code generator comprising: a plurality of autonomous sequential circuits, means for interconnecting said sequential circuits in a plurality of different configurations, each configuration operable to generate randomized digital signals, means for nonlinearly combining the digital signals generated by said sequential circuits, and means responsive to the output of said combining means for randomly controlling said interconnecting means in order to randomly vary the interconnection of said sequential circuits.
Claim 35
Dependent Claim
66 words
A random code generator comprising: a plurality of autonomous sequential circuits each operable to generate randomized digital signals, means for randomly controlling the number of sequential steps taken by such circuits between the generation of successive digital signals, means for nonlinearly combining said digital signals to generate a random key stream, and means operable in response to said random key stream for operating said controlling means.
Claim 36
Dependent Claim
66 words
A random code generator comprising: a plurality of autonomous sequential circuits each operable to generate randomized digital signals, means for randomly controlling the number of sequential steps taken by such circuits between the generation of successive digital signals, means for nonlinearly combining said digital signals to generate a random key stream, and means operable in response to said random key stream for operating said controlling means.
Claim 37
Dependent Claim
67 words
In a random code generator, a random prime generation system comprising: a cyclically operable sequential stepping circuit operable to generate digital bits during an idle mode, means for terminating generation of said stepping circuit, means for generating prime data which corresponds to digital bits stored in said stepping circuit after termination of generation, and means for preventing all digital zeros from being stored as said prime data.
Claim 38
Dependent Claim
67 words
In a random code generator, a random prime generation system comprising: a cyclically operable sequential stepping circuit operable to generate digital bits during an idle mode, means for terminating generation of said stepping circuit, means for generating prime data which corresponds to digital bits stored in said stepping circuit after termination of generation, and means for preventing all digital zeros from being stored as said prime data.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |