Analog signal level detector

Claim 1

An analog signal detector comprising: an up/down counter, said counter having a clock input, an up/down control input, and weighted outputs defining a content of the counter; clock means for applying to said clock input a clock signal having a frequency such that the duration of increase of the counter content from zero to its maximum value significantly exceeds the mean period of an analog signal to be detected; a comparator having an input and having an output for controlling said up/down control input of the counter; a group of switched capacitors each having a first and a second plate, said first plates being connected to the input of the comparator, and a switching control circuit for controlling the switching of said capacitors according to a periodic cycle at the clock signal frequency, said cycle having several phases, and said capacitors having respective values corresponding to the weighted outputs of the counter; a reference voltage source; a multiplexing circuit for applying to each individual capacitor either said analog signal to be detected, or the voltage of said voltage reference source, or an earth potential, said multiplexing circuit being controlled by the switching control circuit and by the outputs of the counter so that it assumes various configurations according to the following conditions: (a) in a precharging phase of said periodic cycle, said capacitors each receive on their second plate the analog signal to be detected, while their first plate is connected to the earth potential; (b) at the end of said precharging phase, the first plates are disconnected from the earth potential so as to avoid any loss of charges stored on these first plates during the precharging phase; (c) in a comparison phase, the second plate of each respective capacitor is connected either to the reference voltage or to the earth potential, depending on whether that output of the counter which has the same weight as the respective capacitor has a value 0 or 1.