Patent US4721686A successfully refreshed from Google Patents.
US4721686A
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Manufacturing integrated circuits containing P-channel MOS transistors and bipolar transistors utilizing boron and arsenic as dopants
Assignee: STMicroelectronics SRL
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Filing: 1987-01-22
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Granted: 1988-01-26
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Expires: 2007-01-22
Abstract
Abstract This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N + type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.
Inventors
- 👤 Claudio Contiero
- 👤 Paola Galbiati
- 👤 Antonio Andreini
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:11
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10P30/21; H10P30/212; H10P32/00; H10P32/10; H10P32/14; H10P32/1404; H10P32/1406; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
123 words
Method for manufacturing integrated electronic devices, in particular high voltage P-channel MOS transistors by forming an epitaxial layer defining a device's main surface, at least a first P-type region in said epitaxial layer and at least a second N-type region in said epitaxial layer, characterized in that for forming said first P-type region a boron implant is performed on said main surface, without masking, and for forming said second N-type region an arsenic implant is performed on selective portions of said device main surface, through a mask, and subsequently a thermal treatment phase is carried out to diffuse implanted boron and arsenic, thereby in said selective portions an interaction between said boron and said arsenic and inhibition of boron diffusion by arsenic occur.
Claim 2
Dependent Claim
123 words
Method for manufacturing integrated electronic devices, in particular high voltage P-channel MOS transistors by forming an epitaxial layer defining a device's main surface, at least a first P-type region in said epitaxial layer and at least a second N-type region in said epitaxial layer, characterized in that for forming said first P-type region a boron implant is performed on said main surface, without masking, and for forming said second N-type region an arsenic implant is performed on selective portions of said device main surface, through a mask, and subsequently a thermal treatment phase is carried out to diffuse implanted boron and arsenic, thereby in said selective portions an interaction between said boron and said arsenic and inhibition of boron diffusion by arsenic occur.
Claim 3
Dependent Claim
41 words
Method according to claim 1, characterized in that is comprises forming an oxide layer with differentiated thickness on said device main surface before said boron implant, then said arsenic implant and further known phases are performed for end manufacturing electronic devices.
Claim 4
Dependent Claim
35 words
Method according to claim 1, including simultaneously manufacturing at least one first electronic device having at least said first P-type region and at least a second electronic device having at least said second N-type region.
Claim 5
Dependent Claim
64 words
Method according to claim 3, characterized in that said at least one first electronic device is a high voltage P-channel MOS transistor, said first P-type region conductivity being a drain extension region and said at least one second device is selected from a group consisting of NPN and PNP transistors, N-channel and P-channel MOS and D-MOS transistors, and integrated resistors formed in N-conductivity regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-01-25 | 1991-07-27 | 1992-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-01-25 | 1995-07-27 | 1996-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-01-25 | 1999-07-27 | 2000-01-26 | $7700.00 | Window Closed / Lapsed |