Sample data acquisition system using microprocessor controlled sequence having FIFO buffer, DAM controller

Claim 2

A data acquisition system comprising: timing means for generating a plurality of timing signals; a plurality of signal conditioner means coupled to said timing means, each of said plurality of signal conditioner means receiving a plurality of analog signals and being responsive to one of said plurality of timing signals for sampling each of said plurality of analog signals at the rate determined by said one of said plurality of timing signals and generating digitized data words representative of the sampled value of said each of said analog signals; interrupt means coupled to said timing means and responsive to said timing signals for generating first coded interrupt signals indicating a highest priority of said plurality of signal conditioner means requiring service; microprocessor means coupled to said interrupt means and responsive to said first coded interrupt signals for generating a plurality of bus signals and coded acknowledge signals, said interrupt means being responsive to said coded acknowledge signals for generating second coded interrupt signals indicating the next highest priority of said plurality of signal conditioner means requiring service; microengine means coupled to said microprocessor means and responsive to said plurality of bus signals for generating a sequence of address signals, said highest priority of said plurality of signal conditioner means being responsive to said sequence of address signals for generating a sequence of said digitized data words, each of said sequence of said digitized data words being representative of the sampled value of said each of said analog signals; first in-first out buffer means coupled to said plurality of signal conditioner means for receiving said sequence of said digitized data words and generating data word signals; direct memory access controller means coupled to said first in-first out means for receiving said data word signals, and generating memory address signals and an address strobe signal; first bus controller means coupled to said direct memory access controller means and responsive to said address strobe signal for generating a request signal; and memory means coupled to said first bus controller means and responsive to said request signal for generating a grant signal; and bus means coupling said direct memory access controller means and said memory means, said first bus controller means being responsive to said grant signal for enabling said memory address signals and said data word signals to be transferred to said memory means.

Claim 3

A data acquisition system comprising: timing means for generating a plurality of timing signals; a plurality of signal conditioner means coupled to said timing means, each of said plurality of signal conditioner means receiving a plurality of analog signals and being responsive to one of said plurality of timing signals for sampling each of said plurality of analog signals at the rate determined by said one of said plurality of timing signals and generating digitized data words representative of the sampled value of said each of said analog signals; interrupt means coupled to said timing means and responsive to said timing signals for generating first coded interrupt signals indicating a highest priority of said plurality of signal conditioner means requiring service; microprocessor means coupled to said interrupt means and responsive to said first coded interrupt signals for generating a plurality of bus signals and coded acknowledge signals, said interrupt means being responsive to said coded acknowledge signals for generating second coded interrupt signals indicating the next highest priority of said plurality of signal conditioner means requiring service; microengine means coupled to said microprocessor means and responsive to said plurality of bus signals for generating a sequence of address signals, said highest priority of said plurality of signal conditioner means being responsive to said sequence of address signals for generating a sequence of said digitized data words, each of said sequence of said digitized data words being representative of the sampled value of said each of said analog signals; first in-first out buffer means coupled to said plurality of signal conditioner means for receiving said sequence of said digitized data words and generating data word signals; direct memory access controller means coupled to said first in-first out means for receiving said data word signals, and generating memory address signals and an address strobe signal; first bus controller means coupled to said direct memory access controller means and responsive to said address strobe signal for generating a request signal; and memory means coupled to said first bus controller means and responsive to said request signal for generating a grant signal, bus means coupling said direct memory access controller means and said memory means, said first bus controller means being responsive to said first grant signal for enabling said first memory address signals and said first data word signals to be transferred to said memory means; said microprocessor means being responsive to said second coded interrupt signals for interrupting said microengine means and generating a second sequence of address signals, a selected one of said plurality of signal conditioners being responsive to said second sequence of address signals for generating a second sequence of said digitized data words, each being representative of said each of said analog values, said direct memory access controller means generating second memory address signals and a second address strobe signal; and second bus controller means coupled to said microprocessor means and responsive to said second address strobe signal for generating a second request signal; said memory means coupled to said second bus controller means and responsive to said second request signal for generating a second grant signal, said second bus controller means being responsive to said second grant signal for enabling said second memory address signals and said data word signals for transfer to said memory means

Claim 4

A data acquisition system comprising: timing means for generating a plurality of timing signals; a plurality of signal conditioner means coupled to said timing means, each of said plurality of signal conditioner means receiving a plurality of analog signals and being responsive to one of said plurality of timing signals for sampling each of said plurality of analog signals at the rate determined by said one of said plurality of timing signals and generating digitized data words representative of the sampled value of said each of said analog signals; interrupt means coupled to said timing means and responsive to said timing signals for generating first coded interrupt signals indicating a highest priority of said plurality of signal conditioner means requiring service; microprocessor means coupled to said interrupt means and responsive to said first coded interrupt signals for generating a plurality of bus signals and coded acknowledge signals, said interrupt means being responsive to said coded acknowledge signals for generating second coded interrupt signals indicating the next highest priority of said plurality of signal conditioner means requiring service; microengine means coupled to said microprocessor means and responsive to said plurality of bus signals for generating a sequence of address signals, said highest priority of said plurality of signal conditioner means being responsive to said sequence of address signals for generating a sequence of said digitized data words, each of said sequence of said digitized data words being representative of the sampled value of said each of said analog signals; first in-first out buffer means coupled to said plurality of signal conditioner means for receiving said sequence of said digitized data words and generating data word signals; direct memory access controller means coupled to said first in-first out means for receiving said data word signals, and generating memory address signals and an address strobe signal; first bus controller means coupled to said direct memory access controller means and responsive to said address strobe signal for generating a request signal; and memory means coupled to said first bus controller means and responsive to said request signal for generating a grant signal, bus means coupling said direct memory access controller means and said memory means, said first bus controller means being responsive to said first grant signal for enabling said first memory address signals and said first data word signals to be transferred to said memory means; said microprocessor means being responsive to said second coded interrupt signals for interrupting said microengine means and generating a second sequence of address signals, a selected one of said plurality of signal conditioners being responsive to said second sequence of address signals for generating a second sequence of said digitized data words, each being representative of said each of said analog values, said direct memory access controller means generating second memory address signals and a second address strobe signal; and second bus controller means coupled to said microprocessor means and responsive to said second address strobe signal for generating a second request signal; said memory means coupled to said second bus controller means and responsive to said second request signal for generating a second grant signal, said second bus controller means being responsive to said second grant signal for enabling said second memory address signals and said data word signals for transfer to said memory means