Insulated dual gate field effect transistor

Claim 1

A semiconductor device having a semiconductor body comprising at least an insulated gate field effect transistor having a surface-adjacent first region, a surface-adjacent channel region of a first conductivity type surrounded at least laterally by the first region, said first region being of a selected conductivity type, a source zone of the second opposite conductivity type adjoining the surface and surrounded within the semiconductor body at least in part by the channel region, a surface-adjacent channel zone between the source zone and the first region and forming part of the channel region, a drain zone of the second conductivity type which is separated by a part of the first region, referred to as the drift region, from the channel region and has a higher doping concentration than that of the first region, an electrically insulating layer located at least on the channel zone and a gate electrode located on the insulating layer above the channel zone, characterized in that a second gate electrode located on the drain side of the channel zone and separated from the first gate electrode is present on the insulating layer above the channel zone adjacent the first gate electrode located on the source side of the channel zone, whereby in the direction from the source zone to the drain zone, the length L 2 of the part of the second gate electrode located above the channel zone and separated therefrom only by said insulating layer is larger than the length L 1 of the part of the first gate electrode located above the channel zone and separated therefrom only by said insulating layer, said device further comprising means for applying a potential difference between said first and second gate electrodes during operation.