Patent US4716318A successfully refreshed from Google Patents.
US4716318A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low pass filter formed in an integrated circuit
Assignee: Toshiba Corp
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Filing: 1986-03-12
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Granted: 1987-12-29
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Expires: 2006-03-12
Abstract
Abstract A low pass filter which has a plurality of NAND gates connected in series. Input signals are input directly to one input terminal of each of the respective NAND gates, respectively. Input signals are input through a plurality of inverters to the NAND gate of the initial stage. The NAND gate of the final stage is connected through even number of inverters to a circuit output node N2. An odd number of inverters are provided between the preceding and following NAND gates.
Inventors
- 👤 Hideharu Koike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:57
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
439 words
A low pass filter apparatus formed in an integrated circuit comprising: an input terminal of said apparatus; an output terminal of said apparatus; a first low pass filter circuit including a first low pass filter circuit input terminal connected to said input terminal of said apparatus, a first low pass filter circuit output terminal, a plurality of series connected NAND gates connected between said first low pass filter circuit input terminal and said first low pass filter circuit output terminal, the first input terminal of each of said NAND gates being directly connected to said first low pass filter circuit input terminal, an even number of inverters connected in series between said first low past filter circuit input terminal and the second input terminal of the first of said series connected NAND gates, an odd number of inverters connected between the output terminal of each of said series connected NAND gates and the second input terminal of the following NAND gate of said series connected NAND gates, and an odd number of inverters connected between the output terminal of the last NAND gate of said series connected NAND gate and said first low pass filter circuit output terminal; a second low pass filter circuit including a second low pass filter circuit input terminal connected to said input terminal of said apparatus, a second low pass filter circuit output terminal, a plurality of series connected NAND gates connected between said second low pass filter circuit input terminal and said second low pass filter circuit output terminal, the first input terminal of each of said NAND gates being directly connected to said second low pass filter circuit input terminal, an even number of inverters connected in series between said second low pass filter circuit input terminal and the second input terminal of the first of said series connected NAND gates, an odd number of inverters connected between the output terminal of each of said series connected NAND gates and the second input terminal of the following NAND gate of said series connected NAND gates, and an odd number of inverters connected between the output terminal of the last NAND gate of said series connected NAND gates and said second low pass filter circuit output terminal; an inverter inserted between said input terminal of said apparatus and said second low pass filter circuit input terminal; and a set/reset type flip-flop circuit having a set input terminal connected to said first low pass filter circuit output terminal, a reset input terminal connected to said second low pass filter circuit output terminal, and an output terminal connected to said output terminal of said apparatus.
Claim 2
Dependent Claim
439 words
A low pass filter apparatus formed in an integrated circuit comprising: an input terminal of said apparatus; an output terminal of said apparatus; a first low pass filter circuit including a first low pass filter circuit input terminal connected to said input terminal of said apparatus, a first low pass filter circuit output terminal, a plurality of series connected NAND gates connected between said first low pass filter circuit input terminal and said first low pass filter circuit output terminal, the first input terminal of each of said NAND gates being directly connected to said first low pass filter circuit input terminal, an even number of inverters connected in series between said first low past filter circuit input terminal and the second input terminal of the first of said series connected NAND gates, an odd number of inverters connected between the output terminal of each of said series connected NAND gates and the second input terminal of the following NAND gate of said series connected NAND gates, and an odd number of inverters connected between the output terminal of the last NAND gate of said series connected NAND gate and said first low pass filter circuit output terminal; a second low pass filter circuit including a second low pass filter circuit input terminal connected to said input terminal of said apparatus, a second low pass filter circuit output terminal, a plurality of series connected NAND gates connected between said second low pass filter circuit input terminal and said second low pass filter circuit output terminal, the first input terminal of each of said NAND gates being directly connected to said second low pass filter circuit input terminal, an even number of inverters connected in series between said second low pass filter circuit input terminal and the second input terminal of the first of said series connected NAND gates, an odd number of inverters connected between the output terminal of each of said series connected NAND gates and the second input terminal of the following NAND gate of said series connected NAND gates, and an odd number of inverters connected between the output terminal of the last NAND gate of said series connected NAND gates and said second low pass filter circuit output terminal; an inverter inserted between said input terminal of said apparatus and said second low pass filter circuit input terminal; and a set/reset type flip-flop circuit having a set input terminal connected to said first low pass filter circuit output terminal, a reset input terminal connected to said second low pass filter circuit output terminal, and an output terminal connected to said output terminal of said apparatus.
Claim 3
Dependent Claim
424 words
A low pass filter apparatus formed in an integrated circuit comprising: an input terminal of said apparatus; an output terminal of said apparatus; a first low pass filter circuit including a first low pass filter circuit input terminal connected to said input terminal of said apparatus, a first low pass filter circuit output terminal, a plurality of series connected NOR gates connected between said first low pass filter circuit input terminal and said first low pass filter circuit output terminal, the first input terminal of each of said NOR gates being directly connected to said first low pass filter circuit input terminal, an even number of inverters connected in series between said first low pass filter circuit input terminal and the second input terminal of the first of said series connected NOR gates, an odd number of inverters connected between the output terminal of each of said series connected NOR gates and the second input terminal of the following NOR gate of said series connected NOR gates, and an odd number of inverters connected between the output terminal of the last NOR gate of said series connected NOR gates and said first low pass filter circuit output terminal; a second low pass filter circuit including a second low pass filter circuit output terminal, a plurality of series connected stages of NOR gates connected between said second low pass filter circuit input terminal and said second low pass filter circuit output terminals, the first input terminal of each of said NOR gates being directly connected to said second low pass filter circuit input terminal, an even number of inverters connected in series between said second low pass filter circuit input terminal and the second input terminal of the first of said series connected NOR gates, an odd number of inverters connected between the output terminal of each of said series connected NOR gates and the second input terminal of the following NOR gate of said series connected NOR gates, and an odd number of inverters connected between the output terminal of the last NOR gate of said series connected NOR gates and said second low pass filter circuit output terminal; an inverter inserted between said input terminal of said apparatus and said second low pass filter circuit input terminal; and a set/reset type flip-flop circuit having a set input terminal connected to said first low pass filter circuit output terminal, a reset terminal connected to said second low pass filter circuit output terminal, and an output terminal connected to said output terminal of said apparatus.
Claim 4
Dependent Claim
424 words
A low pass filter apparatus formed in an integrated circuit comprising: an input terminal of said apparatus; an output terminal of said apparatus; a first low pass filter circuit including a first low pass filter circuit input terminal connected to said input terminal of said apparatus, a first low pass filter circuit output terminal, a plurality of series connected NOR gates connected between said first low pass filter circuit input terminal and said first low pass filter circuit output terminal, the first input terminal of each of said NOR gates being directly connected to said first low pass filter circuit input terminal, an even number of inverters connected in series between said first low pass filter circuit input terminal and the second input terminal of the first of said series connected NOR gates, an odd number of inverters connected between the output terminal of each of said series connected NOR gates and the second input terminal of the following NOR gate of said series connected NOR gates, and an odd number of inverters connected between the output terminal of the last NOR gate of said series connected NOR gates and said first low pass filter circuit output terminal; a second low pass filter circuit including a second low pass filter circuit output terminal, a plurality of series connected stages of NOR gates connected between said second low pass filter circuit input terminal and said second low pass filter circuit output terminals, the first input terminal of each of said NOR gates being directly connected to said second low pass filter circuit input terminal, an even number of inverters connected in series between said second low pass filter circuit input terminal and the second input terminal of the first of said series connected NOR gates, an odd number of inverters connected between the output terminal of each of said series connected NOR gates and the second input terminal of the following NOR gate of said series connected NOR gates, and an odd number of inverters connected between the output terminal of the last NOR gate of said series connected NOR gates and said second low pass filter circuit output terminal; an inverter inserted between said input terminal of said apparatus and said second low pass filter circuit input terminal; and a set/reset type flip-flop circuit having a set input terminal connected to said first low pass filter circuit output terminal, a reset terminal connected to said second low pass filter circuit output terminal, and an output terminal connected to said output terminal of said apparatus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-28 | 1991-06-29 | 1991-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-28 | 1995-06-29 | 1995-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-28 | 1999-06-29 | 1999-12-29 | $7700.00 | Window Closed / Lapsed |