US4712124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Complementary lateral insulated gate rectifiers with matched "on" resistances
Assignee: Philips North America LLC
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Filing: 1986-12-22
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Granted: 1987-12-08
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Expires: 2006-12-22
Abstract
Abstract A complementary Lateral Insulated Gate Rectifier (LIGR) includes two complementary LIGR structures fabricated in adjacent surface-adjoining semiconductor wells of the same conductivity type in a semiconductor substrate. The two LIGR structures are of generally similar configuration, thus simplifying the manufacturing process, and the proposed design additionally permits the n-channel and p-channel LIGR structures to have comparable "on" resistances. The two LIGR structures, otherwise isolated by a portion of the substrate separating the two semiconductor wells, are connected together by a common source electrode. The resulting complementary Lateral Insulated Gate Rectifier features a compact, integrated structure in which the "on" resistances of both the n-channel and p-channel portions of the device are comparable.
Inventors
- 👤 Edward H. Stupp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:05
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/676; H10D12/00; H10D12/411; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
375 words
A complementary Lateral Insulated Gate Rectifier (LIGR), which comprises: a semiconductor substrate of a first conductivity type and having a major surface; first and second adjacent surface-adjoining semiconductor wells of a second conductivity type opposite to that of said first type in said substrate and separated from each other by a portion of said substrate; a first surface-adjoining semiconductor region of the first conductivity type in said first well and a shallower, surface-adjoining first source region of the second conductivity type in said first semiconductor region; a first surface-adjoining drain region of the second conductivity type in said first well and a second, shallower surface-adjoining drain region of the first conductivity type in said first drain region; a first surface-adjoining drain extension region of the first conductivity type in said first well and extending from said first drain region toward said first semiconductor region; an insulating layer on said major surface and having a first insulating layer portion over said first well and covering at least a portion of said first semiconductor region between said first source region and said first drain region; a first gate electrode on said first insulating layer portion, over at least said portion of the first semiconductor region, and insulated from said substrate; a second surface-adjoining source region of the first conductivity type in said second wall; a third surface-adjoining drain region of the first conductivity type in said second well and a fourth, shallower surface-adjoining drain region of the second conductivity type in said third drain region; a second surface-adjoining drain extension region of the first conductivity type in said second well and extending from said third drain region toward said second source region; a second insulating layer portion of said insulating layer on said major surface over said second well and covering at least a portion of said second well between said second source region and said second drain extension region; a second gate electrode on said second insulating layer portion, over at least said portion of said second well, and insulated from said substrate; first and second drain electrodes connected, respectively, to said second and fourth drain regions; and a source electrode connected to said first semiconductor region, said first source region and said second source region.
Claim 2
Dependent Claim
375 words
A complementary Lateral Insulated Gate Rectifier (LIGR), which comprises: a semiconductor substrate of a first conductivity type and having a major surface; first and second adjacent surface-adjoining semiconductor wells of a second conductivity type opposite to that of said first type in said substrate and separated from each other by a portion of said substrate; a first surface-adjoining semiconductor region of the first conductivity type in said first well and a shallower, surface-adjoining first source region of the second conductivity type in said first semiconductor region; a first surface-adjoining drain region of the second conductivity type in said first well and a second, shallower surface-adjoining drain region of the first conductivity type in said first drain region; a first surface-adjoining drain extension region of the first conductivity type in said first well and extending from said first drain region toward said first semiconductor region; an insulating layer on said major surface and having a first insulating layer portion over said first well and covering at least a portion of said first semiconductor region between said first source region and said first drain region; a first gate electrode on said first insulating layer portion, over at least said portion of the first semiconductor region, and insulated from said substrate; a second surface-adjoining source region of the first conductivity type in said second wall; a third surface-adjoining drain region of the first conductivity type in said second well and a fourth, shallower surface-adjoining drain region of the second conductivity type in said third drain region; a second surface-adjoining drain extension region of the first conductivity type in said second well and extending from said third drain region toward said second source region; a second insulating layer portion of said insulating layer on said major surface over said second well and covering at least a portion of said second well between said second source region and said second drain extension region; a second gate electrode on said second insulating layer portion, over at least said portion of said second well, and insulated from said substrate; first and second drain electrodes connected, respectively, to said second and fourth drain regions; and a source electrode connected to said first semiconductor region, said first source region and said second source region.
Claim 3
Dependent Claim
68 words
A complementary Lateral Insulated Gate Rectifier (LIGR) as in claim 1, further comprising a fifth surface-adjoining drain region of the second conductivity type in said first drain region, contacting said second drain region, and connected to said first drain electrode, and a sixth surface-adjoining drain region of the first conductivity type in said third drain region, contacting said fourth drain region, and connected to said second drain electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-07 | 1991-06-08 | 1991-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-07 | 1995-06-08 | 1995-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-07 | 1999-06-08 | 1999-12-08 | $7700.00 | Window Closed / Lapsed |