Formation of buried diffusion devices

Claim 2

A process for reducing collector parasitic resistance in a bipolar transistor having a collector, base and emitter, suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming at least one lightly doped N - region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) forming an N + region in the bottom of said trench; (e) driving said N + region to a depth of about one-half the width of the device; (f) etching said trench past said N + region into said P-type substrate region; (g) forming a P + region in the bottom of said trench; and (h) refilling said trench with insulating material.

Claim 3

The process of claim 1 in which said N + region is formed by implantation.

Claim 4

The process of claim 2 in which said N + region is implanted at a dose of about 1×10 15 to 2×10 16 cm -2 , employing an implant energy of about 20 to 200 keV.

Claim 5

The process of claim 3 in which said implantation employs an element selected from the group consisting of arsenic, phosphorus and antimony.

Claim 6

The process of claim 1 in which said trench is initially etched to a depth of about 1.2 to 1.5 μm for devices of widths of about 2 to 3 μm.

Claim 7

The process of claim 1 in which said N + region is driven by diffusion at a temperature ranging from about 950° to 1100° C. for a period of time ranging from about 1 to 10 hours.

Claim 8

The process of claim 1 in which said trench is etched at least about 0.5 μm past said diffused region.

Claim 9

The process of claim 1 in which said P + region is formed by implantation.

Claim 10

The process of claim 8 in which said P + region is implanted at a dose of about 10 13 to 10 15 cm -2 , employing an implant energy of about 25 to 75 keV.

Claim 11

The process of claim 9 in which said implantation employs boron.

Claim 12

The process of claim 1 wherein said insulating material comprises thermally grown silicon dioxide, deposited doped or undoped silicon dioxide, silicon nitride, polysilicon, aluminum oxide, or combinations thereof.

Claim 13

The process of claim 1 in which following step (c), the following process occurs: (c1) oxidizing the walls of said trench; (c2) anisotropically etching to remove oxide formed on the bottom of said trench; (c3) etching said trench an additional amount to expose silicon along a portion of said walls of said trench; and (d') diffusing an N-type species into said exposed silicon in said trench to form an N + region.

Claim 14

The process of claim 12 in which said walls of said trench are oxidized by a wet thermal process, employing a temperature of about 900° to 1100° C. for a period of time necessary to grow an oxide having a thickness of about 1000 to 3000 Angstroms.

Claim 15

The process of claim 12 wherein said trench is etched an additional amount of about 0.5 to 1 μm.

Claim 16

The process of claim 12 wherein said N + region is formed by decomposition of PH 3 or POCl 3 at a temperature ranging from about 850° to 1050° C. for a period of time ranging from about 10 minutes to 1 hour.

Claim 17

The process of claim 12 in which the following step (d'), the following processing occurs: (d1) forming a metal silicide on the exposed walls of said trench, on said N + diffused region; and (d2) anisotropically etching the bottom of said trench to remove silicon formed thereon.

Claim 18

The process of claim 16 in which said silicide comprises a refractory metal silicide.

Claim 19

The process of claim 17 in which the refractory metal comprises a member selected from the group consisting of tungsten, titanium, tantalum and molybdenum.

Claim 20

A process for reducing collector parasitic resistance in a bipolar transistor having a collector, base and emitter and suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming a lightly doped N - region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) forming an N + region in the bottom of said trench by ion implantation, employing a species selected from the group consisting of arsenic, phosphorus or antimony and implanting at a dose of about 1×10 15 to to 2×10 16 cm -2 and an implant energy of about 20 to 200 keV; (e) driving said N + region by diffusion to a depth of about one-half the width of the device; (f) etching said trench past said diffused region; (g) forming a P + region in the bottom of said trench by ion implantation, employing boron and implanting at a dose of about 10 13 to 10 15 cm -2 and a implant energy of about 25 to 75 keV; and (h) refilling said trench with insulating material.

Claim 21

A process for reducing collector parasitic resistance in a bipolar transistor having a collector, base and emitter and suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming a lightly doped N - region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) forming an N + region in the bottom of said trench by ion implantation, employing a species selected from the group consisting of arsenic, phosphorus or antimony and implanting at a dose of about 1×10 15 to to 2×10 16 cm -2 and an implant energy of about 20 to 200 keV; (e) driving said N + region by diffusion to a depth of about one-half the width of the device; (f) etching said trench past said diffused region; (g) forming a P + region in the bottom of said trench by ion implantation, employing boron and implanting at a dose of about 10 13 to 10 15 cm -2 and a implant energy of about 25 to 75 keV; and (h) refilling said trench with insulating material.

Claim 22

The process of claim 19 in which said trench is initially etched to a depth of about 1.2 to 1.5 μm for devices of widths of about 2 to 3 μm.

Claim 23

The process of claim 19 in which said N + region is driven by diffusion at a temperature ranging from about 950° to 1100° C. for a period of time ranging from about 1 to 10 hours.

Claim 24

The process of claim 19 in which said trench is etched at least about 0.5 μm past said diffused region.

Claim 25

The process of claim 19 in which said P + region is formed by implantation.

Claim 26

The process of claim 19 wherein said insulating material comprises thermally grown silicon dioxide, deposited doped or undoped silicon dioxide, silicon nitride, polysilicon, aluminum oxide, or combinations thereof.

Claim 27

A process for reducing collector resistance in a bipolar transistor having a collector, base and emitter and suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming a lightly doped N region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) oxidizing the walls of said trench; (e) anisotropically etching to remove oxide formed on the bottom of said trench; (f) etching said trench an additional amount within said N - region to expose silicon along a portion of the walls of said trench; (g) diffusing an N-type species into said exposed silicon of said trench to form a N + region; (h) driving said N + region by diffusion to a depth of about one-half the width of the device; (i) etching said trench past said diffused region into said P-type substrate; (j) forming a P + region in the bottom of said trench; and (k) refilling said trench with insulating material.

Claim 28

A process for reducing collector resistance in a bipolar transistor having a collector, base and emitter and suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming a lightly doped N region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) oxidizing the walls of said trench; (e) anisotropically etching to remove oxide formed on the bottom of said trench; (f) etching said trench an additional amount within said N - region to expose silicon along a portion of the walls of said trench; (g) diffusing an N-type species into said exposed silicon of said trench to form a N + region; (h) driving said N + region by diffusion to a depth of about one-half the width of the device; (i) etching said trench past said diffused region into said P-type substrate; (j) forming a P + region in the bottom of said trench; and (k) refilling said trench with insulating material.

Claim 29

The process of claim 25 in which said trench is initially etched to a depth of about 1.2 to 1.5 μm for devices of widths of about 2 to 3 μm.

Claim 30

The process of claim 25 in which said N + region is driven by diffusion at a temperature ranging from about 950° to 1100° C. for a period of time ranging from about 1 to 10 hours.

Claim 31

The process of claim 25 in which said trench is etched at least about 0.5 μm past said diffused region.

Claim 32

The process of claim 25 in which said P + region is formed by implantation.

Claim 33

The process of claim 29 in which said P + region is implanted at a dose of about 10 13 to 10 15 cm -2 , employing an implant energy of about 25 to 75 keV.

Claim 34

The process of claim 30 in which said implantation employs boron.

Claim 35

The process of claim 25 wherein said insulating material comprises thermally grown silicon dioxide, deposited doped or undoped silicon dioxide, silicon nitride, polysilicon, aluminum oxide, or combinations thereof.

Claim 36

The process of claim 25 in which said walls of said trench are oxidized by a wet thermal process, employing a temperature of about 900° to 1100° C. for a period of time necessary to grow an oxide having a thickness ranging from about 1000 to 3000 Angstroms.

Claim 37

The process of claim 25 wherein said trench is etched an additional amount of about 0.5 to 1 μm.

Claim 38

The process of claim 25 wherein said N + region is formed by decomposition of PH 3 or POCl 3 at a temperature ranging from about 850° to 1050° C. for a period of time ranging from about 10 minutes to 1 hour.

Claim 39

A process of reducing collector resistance in a bipolar transistor having a collector, base and emitter and suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming a lightly doped N - region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) oxidizing the walls of said trench; (e) anisotropically etching to remove oxide formed on the bottom of said trench; (f) etching said trench an additional amount within said N - region to expose silicon along a portion of the walls of said trench; (g) diffusing an N-type species into the exposed silicon of said trench to form an N + region; (h) driving said N + region by diffusion to a depth of about one-half the width of the device; (i) forming a metal silicide on the exposed walls of said trench, on said N + diffused region; (j) anisotropically etching the bottom of said trench to remove the silicide formed thereon; (k) etching said trench past said diffused region into said P-type substrate; (l) forming a P + region in the bottom of said trench; and (m) refilling said trench with insulating material.

Claim 40

A process of reducing collector resistance in a bipolar transistor having a collector, base and emitter and suitable contacts and metallization thereto, the process for forming said collector comprising: (a) providing a P-type substrate; (b) forming a lightly doped N - region in the P-type substrate; (c) etching a vertical trench in said N - region to define the perimeter of said transistor; (d) oxidizing the walls of said trench; (e) anisotropically etching to remove oxide formed on the bottom of said trench; (f) etching said trench an additional amount within said N - region to expose silicon along a portion of the walls of said trench; (g) diffusing an N-type species into the exposed silicon of said trench to form an N + region; (h) driving said N + region by diffusion to a depth of about one-half the width of the device; (i) forming a metal silicide on the exposed walls of said trench, on said N + diffused region; (j) anisotropically etching the bottom of said trench to remove the silicide formed thereon; (k) etching said trench past said diffused region into said P-type substrate; (l) forming a P + region in the bottom of said trench; and (m) refilling said trench with insulating material.

Claim 41

The process of claim 36 in which said trench is initially etched to a depth of about 1.2 to 1.5 μm for devices of widths of about 2 to 3 μm.

Claim 42

The process of claim 36 in which said N + region is driven by diffusion at a temperature ranging from about 950° to 1100° C. for a period of time ranging from about 1 to 10 hours.

Claim 43

The process of claim 36 in which said trench is etched at least about 0.5 μm past said diffused region.

Claim 44

The process of claim 36 in which said P + region is formed by implantation.

Claim 45

The process of claim 40 in which said P + region is implanted at a dose of about 10 13 to 10 15 cm -2 , employing an implant energy of about 25 to 75 keV.

Claim 46

The process of claim 41 in which said implantation employs boron.

Claim 47

The process of claim 36 wherein said insulating material comprises thermally grown silicon dioxide, deposited doped or undoped silicon dioxide, silicon nitride, polysilicon, aluminum oxide, or combinations thereof.

Claim 48

The process of claim 36 in which said walls of said trench are oxidized by a wet thermal process, employing a temperature of about 900° to 1100° C. for a period of time necessary to grow an oxide having a thickness ranging from about 1000 to 3000 Angstroms.

Claim 49

The process of claim 36 wherein said trench is etched an additional amount of about 0.5 to 1 μm.

Claim 50

The process of claim 36 wherein said N + region is formed by decomposition of PH 3 or POCl 3 at a temperature ranging from about 850° to 1050° C. for a period of time ranging from about 10 minutes to 1 hour.

Claim 51

The process of claim 36 in which said metal silicide comprises a refractory metal silicide.

Claim 52

The process of claim 47 in which the refractory metal comprises a member selected from the group consisting of tungsten, titanium, tantalum and molybdenum.