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US4707897A
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Monolithic semiconductor integrated circuit ferroelectric memory device, and methods of fabricating and utilizing same
Assignee: Ramtron International Corp
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Filing: 1980-03-24
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Granted: 1987-11-24
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Expires: 2000-03-24
Abstract
Abstract A monolithic semiconductor integrated circuit-ferroelectric device is disclosed together with the method of manufacturing same. The ferrelectric device preferably consists of a layer of stable ferroelectric potassium nitrate disposed between electrical contacts positioned on opposite surfaces of the ferroelectric layer. The ferroelectric layer has a thickness of less than 110 microns, and preferably falling within a range of from 100 Angstrom units to 5,000 Angstrom units. The process of manufacturing the monolithic structure is multi-stepped and is particularly adapted for fabricating a potassium nitrate ferroelectric memory on a semiconductor integrated circuit.
Inventors
- 👤 George A. Rohrer
- 👤 Larry McMillan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:06
CPC Classifications
H; H01; H01G; H01G7/00; H01G7/02; Y; Y10; Y10T; Y10T29/00; Y10T29/43; Y10T29/435
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
88 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming a first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductor dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; and G. applying conductive material to the bonding and interconnect pads.
Claim 2
Independent Claim
88 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming a first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductor dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; and G. applying conductive material to the bonding and interconnect pads.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 4
Dependent Claim
17 words
The method of claim 2 wherein said ferroelectric layer has a thickness of less than 110 microns.
Claim 5
Dependent Claim
24 words
The method of claim 2 wherein said ferroelectric layer has a thickness within a range of from 100 Angstrom units to 5,000 Angstrom units.
Claim 6
Dependent Claim
31 words
The method of claim 2 wherein said ferroelectric layer has a thickness of less than 1 micron and comprises Phase III potassium nitrate which is stable at standard temperature and pressure.
Claim 7
Dependent Claim
15 words
The method of claim 1 wherein said first layer interconnections are composed of doped polysilicon.
Claim 8
Dependent Claim
24 words
The method of claim 1 wherein said non-semiconductor dielectric is selected from the group consinting of low temperature glass, silicon nitride and sputtered dielectrics.
Claim 9
Dependent Claim
15 words
The method of claim 1 wherein said first layer interconnections are composed of a metal.
Claim 10
Dependent Claim
21 words
The method of claim 1 wherein more than one ferroelectric memory device array is functionally connected to said semiconductor integrated circuit.
Claim 11
Dependent Claim
47 words
The method of claim 1 wherein a plurality of said ferroelectric memory device arrays are stacked on the semiconductor integrated circuit interconnects such that more than one ferroelectric memory device arrays are layered on top of each other and subsequently all connected to said semiconductor integrated circuit.
Claim 12
Dependent Claim
41 words
The method of claim 1 wherein: said ferroelectric memory device is located on the same planar surface as said semiconductor integrated circuit; and said step B of depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein is omitted.
Claim 13
Dependent Claim
15 words
The method of claim 11 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 14
Dependent Claim
17 words
The method of claim 12 wherein said ferroelectric layer has a thickness of less than 110 microns.
Claim 15
Dependent Claim
24 words
The method of claim 12 wherein said ferroelectric layer has a thickness within a range of from 100 Angstrom units to 5,000 Angstrom units.
Claim 16
Dependent Claim
23 words
The method of claim 12 wherein said ferroelectric layer has a thickness of less than 1 micron and comprises Phase III potassium nitrate.
Claim 17
Independent Claim
132 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; G. depositing a conductive layer and forming a top electrode; H. depositing a top non-semiconductor dielectric layer uniformly; I. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and I. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and J. applying conductive material to the bonding and interconnect pads.
Claim 18
Independent Claim
132 words
A method of fabricating a monolithic semiconductor integrated circuit and ferroelectric memory device comprising: A. forming first layer interconnects on the surface of a semiconductor integrated circuit; B. depositing a non-semiconductor dielectric and cutting interconnect and bonding pad vias therein; C. depositing a conductive layer and forming a bottom electrode; D. depositing a second non-semiconductive dielectric and forming vias therein; E. applying a ferroelectric layer; F. filling any imperfections in said ferroelectric layer with insulative material; G. depositing a conductive layer and forming a top electrode; H. depositing a top non-semiconductor dielectric layer uniformly; I. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and I. removing said top non-semiconductor dielectric layer from the bonding and interconnect pads; and J. applying conductive material to the bonding and interconnect pads.
Claim 19
Dependent Claim
15 words
The method of claim 16 wherein said ferroelectric layer substantially comprises Phase III potassium nitrate.
Claim 20
Dependent Claim
17 words
The method of claim 17 wherein said ferroelectric layer has a thickness of less than 110 microns.
Claim 21
Dependent Claim
24 words
The method of claim 17 wherein said ferroelectric layer has a thickness within a range of from 100 Angstrom units to 5,000 Angstrom units.
Claim 22
Dependent Claim
23 words
The method of claim 17 wherein said ferroelectric layer has a thickness of less than 1 micron and comprises Phase III potassium nitrate.
Claim 23
Dependent Claim
15 words
The method of claim 16 wherein said first layer interconnections are composed of doped polysilicon.
Claim 24
Dependent Claim
24 words
The method of claim 16 wherein said non-semiconductor dielectric is selected from the group consisting of low temperature glass, silicon nitrate and sputtered dielectrics.
Claim 25
Dependent Claim
15 words
The method of claim 16 wherein said first layer interconnections are composed of a metal.
Claim 26
Dependent Claim
33 words
The method of claim 16 wherein said top electrode is formed by defining the top conductive layer by photoresist techniques and back sputtering said top conductive layer until said top electrode is defined.
Claim 27
Dependent Claim
20 words
The method of claim 24 wherein said top conductive layer is partially etched before subjecting it to said back sputtering.
Claim 28
Independent Claim
14 words
A device fabricated according to the method of any one of the preceding claims.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-23 | 1991-05-25 | 1991-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-23 | 1995-05-25 | 1995-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-23 | 1999-05-25 | 1999-11-24 | $7700.00 | Window Closed / Lapsed |