Patent US4707808A successfully refreshed from Google Patents.
US4707808A
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Small size, high speed GaAs data latch
Assignee: Conexant Systems LLC
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Filing: 1985-04-26
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Granted: 1987-11-17
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Expires: 2005-04-26
Abstract
Abstract The invention provides small size, high speed data latches comprising memory cells that are fabricated according to a Gallium Arsenide (GaAs) process. The memory cells are implemented by a relatively few number of depletion metal semiconductor field effect transistors (MESFETs), saturated resistors and diodes. A common gate MESFET is utilized in each memory cell configuration as part oif a non-inverting positive feedback path to provide the gain necessary for bistable operation.
Inventors
- 👤 Gary L. Heimbigner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:42
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
246 words
A GaAs data latch memory cell having a data node at which binary information is stored, said memory cell comprising: a source of binary information input signal; a first multi-terminal depletion MESFET device having source and drain conduction path terminals connected to apply a binary information input signal from said source of binary information input signals to said data node, said first multi-terminal device having a control terminal connected to receive an address signal by which to selectively control the conductivity of said first device, a source for a first voltage signal, a second multi-terminal depletion MESFET device of the common gate type having source and drain conduction path terminals connected to apply said first voltage signal to said data node for preserving the level of the binary state of the information signal stored at said data node for static operation, said second multi-terminal device having a control terminal connected to receive a fixed reference voltage control signal, and a third multi-terminal depletion MESFET device having source and drain conduction path terminals connected to supply said first voltage signal to said second multi-terminal device, said third multi-terminal device having a control terminal connected to said data node by which to control the conductivity of said third device, said third device being connected as a source follower, said second and third devices being interconnected to establish a non-inverting positive feedback path for providing voltage gain to the information signal stored at said data node for bistable operation.
Claim 2
Dependent Claim
246 words
A GaAs data latch memory cell having a data node at which binary information is stored, said memory cell comprising: a source of binary information input signal; a first multi-terminal depletion MESFET device having source and drain conduction path terminals connected to apply a binary information input signal from said source of binary information input signals to said data node, said first multi-terminal device having a control terminal connected to receive an address signal by which to selectively control the conductivity of said first device, a source for a first voltage signal, a second multi-terminal depletion MESFET device of the common gate type having source and drain conduction path terminals connected to apply said first voltage signal to said data node for preserving the level of the binary state of the information signal stored at said data node for static operation, said second multi-terminal device having a control terminal connected to receive a fixed reference voltage control signal, and a third multi-terminal depletion MESFET device having source and drain conduction path terminals connected to supply said first voltage signal to said second multi-terminal device, said third multi-terminal device having a control terminal connected to said data node by which to control the conductivity of said third device, said third device being connected as a source follower, said second and third devices being interconnected to establish a non-inverting positive feedback path for providing voltage gain to the information signal stored at said data node for bistable operation.
Claim 3
Dependent Claim
70 words
The data latch memory cell recited in claim 1, further including a fourth depletion MESFET multi-terminal device coupled to said data node to provide an indication of the binary state of the information signal stored at said data node, said fourth multi-terminal device having a control terminal connected to receive the first voltage signal supplied by said third multi-terminal device by which to control the conductivity of said fourth device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-16 | 1991-05-18 | 1991-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-16 | 1995-05-18 | 1995-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-16 | 1999-05-18 | 1999-11-17 | $7700.00 | Window Closed / Lapsed |