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US4707666A
Expired / Lapsed
US
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Frequency demodulator circuit with zero-crossing counter
Assignee: TDK Micronas GmbH
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Filing: 1986-07-15
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Granted: 1987-11-17
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Expires: 2006-07-15
Abstract
Abstract A digital frequency demodulator circuit works on the principle of determining the number of zero crossings of a band-limited input signal in a given period of time, in corresponding prior art analog circuits. The circuit includes an analog-to-digital converter, three delay elements, two edge detectors, an up/down counter, two arcsin read-only memories, a 1/2 multiplier and a multiple adder.
Inventors
- 👤 Heinrich Pfeifer
- 👤 Rainer Schweer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:28
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/006; H03D2200/00; H03D2200/0041; H03D2200/005; H03D2200/0054; H03D2200/0056; H03D2200/0064
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
269 words
A frequency demodulator circuit comprising: an analog to digital converter receiving an input signal to be demodulated and clocked by a sampling signal at a first frequency; a quadrant detector having its input connected to the output of said analog-to-digital converter; first delay means having its input coupled to said analog-to-digital converter output; second delay means having its input coupled to said analog-to-digital converter output; third delay means having its input coupled to the output of said second delay means; a first edge detector coupled to the sign bit of the output of said second delay means output; a second edge detector coupled to a sign bit of the output of said third delay means; an up/down counter having an up input coupled to the output of said first edge detector and having a down input coupled to the output of said second edge detector; means for multiplying the output of said up/down counter by 1/2; first arcsin memory means having address inputs coupled to the output of said first delay means and having data outputs; second arcsin memory means having address inputs coupled to the output of said third delay means and having data outputs; a multiple adder for adding the output of said multiplying means to said first arcsin memory means data outputs combined with the outputs of said quadrant detector and to said second arcsin memory means data outputs combined with the output of said first delay means; and a decimator having inputs coupled to the output of said multiple adder, said decimator being clocked by said sampling signal and providing a digital demodulated output signal.
Claim 2
Dependent Claim
269 words
A frequency demodulator circuit comprising: an analog to digital converter receiving an input signal to be demodulated and clocked by a sampling signal at a first frequency; a quadrant detector having its input connected to the output of said analog-to-digital converter; first delay means having its input coupled to said analog-to-digital converter output; second delay means having its input coupled to said analog-to-digital converter output; third delay means having its input coupled to the output of said second delay means; a first edge detector coupled to the sign bit of the output of said second delay means output; a second edge detector coupled to a sign bit of the output of said third delay means; an up/down counter having an up input coupled to the output of said first edge detector and having a down input coupled to the output of said second edge detector; means for multiplying the output of said up/down counter by 1/2; first arcsin memory means having address inputs coupled to the output of said first delay means and having data outputs; second arcsin memory means having address inputs coupled to the output of said third delay means and having data outputs; a multiple adder for adding the output of said multiplying means to said first arcsin memory means data outputs combined with the outputs of said quadrant detector and to said second arcsin memory means data outputs combined with the output of said first delay means; and a decimator having inputs coupled to the output of said multiple adder, said decimator being clocked by said sampling signal and providing a digital demodulated output signal.
Claim 3
Dependent Claim
73 words
A frequency demodulator circuit in accordance with claim 1, wherein: said first delay means and said third delay means each provided a delay equal to k times the period of said sampling signal, where k is equal to the integral ratio of the frequency of said sampling signal to the frequency of a clock signal at the pulse repetition rate of which the digital words of said demodulated signal are to be processed.
Claim 4
Dependent Claim
19 words
A frequency demodulator circuit in accordance with claim 2, wherein: said decimator is further clocked by said clock signal.
Claim 5
Dependent Claim
24 words
A frequency demodulator circuit in accordance with claim 2, wherein: said second delay means provides a delay equal to that of said quadrant detector.
Claim 6
Dependent Claim
19 words
A frequency demodulator circuit in accordance with claim 1, wherein: said input signal is band limited and amplitude normalized.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-16 | 1991-05-18 | 1991-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-16 | 1995-05-18 | 1995-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-16 | 1999-05-18 | 1999-11-17 | $7700.00 | Window Closed / Lapsed |