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EP0146652A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

A digital demodulator for digitized frequency-modulated signals

Assignee: TDK Micronas GmbH
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Filing: 1983-12-24
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Granted: —
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Expires: 2003-12-24
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Abstract

Abstract Translated from German Die digitalisierten FM-Signale (fm) sind der Abtasthalteschaltung (ah) zugeführt, die von der ersten Abtaststufe (d1) zur Abtastung mit dem zweiten Abtastsignal (a2) gefolgt ist, wobei deren Frequenz (f2) ganzzahlig-vielfach höher als die Frequenz (f1) des ersten Abtastsignals (a1) ist. Der Ausgang von (d1) liegt am Eingang des von (a2) getakteten Interpolationsfilters (ti), dessen Ausgang mittels der zweiten Abtaststufe (d2) vom zweiten Abtastsignal (a2) abgetastet wird. Deren Ausgang liegt am jeweiligen Eingang der Nulldurchgangdetektoren (n1, n2), die jeweils das entsprechende gruppenlaufzeit-gesteuerte Monoflop (m1, m2) ansteuern. Deren Ausgangssignal wird mit dem Mittelwertkompensationssignal (mk) im Addierer (ad1) aufaddiert und sein Ausgangssignal mittels der Abtaststufe (d3) vom zweiten Abtastsignal (a2) abgetastet und dem digitalen Konversionsfilter (kf) zugeführt, das seinerseits mit den drei Abtastsignalen (a1,a2,a3) getaktet ist. Dabei ist die Frequenz (f3) von (a3) ganzzahlig-vielfach kleiner als die Frequenz (f2) von (a2). The digitized FM signals (fm) are fed to the sample and hold circuit (ah), which is followed by the first sampling stage (d1) for sampling with the second sampling signal (a2), the frequency (f2) of which is an integer many times higher than the frequency ( f1) of the first scanning signal (a1). The output of (d1) is at the input of the interpolation filter (ti) clocked by (a2), the output of which is sampled by the second sampling signal (a2) by means of the second sampling stage (d2). Their output is at the respective input of the zero crossing detectors (n1, n2), which each control the corresponding group delay-controlled monoflop (m1, m2). Their output signal is added to the mean value compensation signal (mk) in the adder (ad1) and its output signal is sampled by the second sampling signal (a2) by means of the sampling stage (d3) and fed to the digital conversion filter (kf), which in turn contains the three sampling signals (a1, a2 , a3) is clocked. The frequency (f3) of (a3) is an integer many times smaller than the frequency (f2) of (a2).

Inventors

  • 👤 Edmund Dipl.-Ing. Zähringer
  • 👤 Peotr Baker
  • 👤 Rolf Dipl.-Ing. Zettel

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 15:24
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/006; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1566; H03D2200/00; H03D2200/0041; H03D2200/005; H03D2200/0054; H03D2200/0056; H03D2200/0058; H03D2200/006; H03D2200/0064

Claims Analysis

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References Cited (Backward Citations)

EP0066229A1 Cited
WO1983001159A1 Cited
EP0099142A2 Cited

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