Arithmetic and logic unit with overflow indicator

Claim 1

Arithmetic and logic unit comprising: a plurality of switching cells each cell being capable of performing addition and having the rank i, where i=1, 2, . . . (i+1) . . . (n-1), in which the rank (n-1) is the highest; a control bus with each cell being connected to said control bus so as to be simultaneously controlled in order to define a determined arithmetic or logic operating mode of the unit, in which: a cell of rank i has an input to receive a bit of rank i of a first number A, an input to receive a bit of the same rank i of a second number B, and has an output for a carry and for a result; a cell of rank i+1 having its carry input connected to the carry output of the cell having the rank i; a cell of highest rank receiving on its cell inouts a sign bit of the first number B and a sign bit of the second number B; and an overflow test circuit for supplying a positive overflow signal and a negative overflow signal, wherein the overflow test circuit comprises three inputs respectively connected to the carry output of the highest ranking cell and to the carry and result outputs of said highest ranking cell.