US4592008A
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Overflow detector for algebraic adders
Assignee: ITT Inc
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Filing: 1983-01-28
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Granted: 1986-05-27
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Expires: 2003-01-28
Abstract
Abstract An MOS high-speed overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder per digit which provides a sum signal (s) and a carry signal (c) consists of a complex gate (k) made up of three two-input AND elements (u1, u2, u3). The outputs of the three AND elements are NORed. The two inputs of the first AND element (u1) are fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively. The two inputs of the second AND element (U2) are fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) of the full adder (av) of the sign digit, respectively. The two inputs of the third AND element (u3) are fed with the inverted sum signal (vs) and the inverted sign signal (va) of the first binary number (a), respectively.
Inventors
- 👤 Guido H. Nopper
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/499; G06F7/49905; G06F7/4991
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
167 words
Insulated-gate field-effect transistor (MOS) integrated overflow detector for algebraic adders which add two binary numbers (a, b) in two's complement notation and contain one full adder per digit which provides a sum signal and a carry signal, comprising: a complex gate (k) consisting of three two-input AND elements (u1, u2, u3), with the outputs of the three AND elements NORed, the two inputs of the first AND element (u1) being fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively, the two inputs of the second AND element (u2) respectively being fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) provided by the full adder (av) of the sign digits, and the two inputs of the third AND element (u3) being fed with the inverted sum signal (vs) and with the inverted sign signal (va) of the first binary number (a), respectively.
Claim 2
Dependent Claim
167 words
Insulated-gate field-effect transistor (MOS) integrated overflow detector for algebraic adders which add two binary numbers (a, b) in two's complement notation and contain one full adder per digit which provides a sum signal and a carry signal, comprising: a complex gate (k) consisting of three two-input AND elements (u1, u2, u3), with the outputs of the three AND elements NORed, the two inputs of the first AND element (u1) being fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively, the two inputs of the second AND element (u2) respectively being fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) provided by the full adder (av) of the sign digits, and the two inputs of the third AND element (u3) being fed with the inverted sum signal (vs) and with the inverted sign signal (va) of the first binary number (a), respectively.
Claim 3
Dependent Claim
135 words
An overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder for the sign digit and wherein, in positive logic said full adder of the sign digit provides the signals va·vb, va+vb, vs, and vs, where va is the sign signal of the first binary number (a), vb is the sign signal of the second binary number (b), vs is the sum signal and vs is the inverted sum signal said detector comprising: a complex gate (k1) comprising two two-input OR elements having their outputs NANDed, the signals va+vb and vs being applied to one of the two OR elements, and the signals va·vb and vs being applied to the other OR element, the output of said complex gate providing an inverted overflow signal (fl).
Claim 4
Dependent Claim
135 words
An overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder for the sign digit and wherein, in positive logic said full adder of the sign digit provides the signals va·vb, va+vb, vs, and vs, where va is the sign signal of the first binary number (a), vb is the sign signal of the second binary number (b), vs is the sum signal and vs is the inverted sum signal said detector comprising: a complex gate (k1) comprising two two-input OR elements having their outputs NANDed, the signals va+vb and vs being applied to one of the two OR elements, and the signals va·vb and vs being applied to the other OR element, the output of said complex gate providing an inverted overflow signal (fl).
Claim 5
Dependent Claim
135 words
An overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder for the sign digit and wherein, in positive logic, said full adder of the sign digit provides the signals va·vb, va+vb, vs, and vs, where va is the sign signal of the first binary number (a), vb is the sign signal fo the second binary number (b), vs is the sum signal and vs is the inverted sum signal said detector comprising: a complex gate (k2) comprising two two-input AND elements having their outputs NORed, the signals va+vb and vs being applied to one of the two AND elements, and the signals va·vb and vs being applied to the other AND element, the output of said complex gate providing an inverted overflow signal (fl).
Claim 6
Dependent Claim
135 words
An overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder for the sign digit and wherein, in positive logic, said full adder of the sign digit provides the signals va·vb, va+vb, vs, and vs, where va is the sign signal of the first binary number (a), vb is the sign signal fo the second binary number (b), vs is the sum signal and vs is the inverted sum signal said detector comprising: a complex gate (k2) comprising two two-input AND elements having their outputs NORed, the signals va+vb and vs being applied to one of the two AND elements, and the signals va·vb and vs being applied to the other AND element, the output of said complex gate providing an inverted overflow signal (fl).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |