Acceleration and deceleration control system

Claim 2

An acceleration and deceleration system for progressively increasing a feed speed up to a command speed and for progressively reducing the feed speed, comprising: a linear acceleration and deceleration circuit operatively connected to receive input data representing a feed speed and a displacement, for effecting a linear acceleration and deceleration computation on the input data to produce an output signal; and an exponential acceleration and deceleration circuit, operatively connected to receive the output signal from said linear acceleration and deceleration circuit, for effecting an exponential acceleration and deceleration computation on the output signal to produce a speed command signal.

Claim 3

An acceleration/deceleration system for at least one of increasing a feed speed up to a command speed and reducing the feed speed in dependence upon feed speed and displacement signals, comprising: an interpolator, operatively connected to receive the feed speed and displacement signals, for computing and issuing interpolation data on a plurality of axes in dependence upon the feed signal and the displacement signal; a linear acceleration and deceleration circuit, operatively connected to receive the interpolation data issued from said interpolator on each axis per one sampling cycle, for effecting a linear acceleration and deceleration computation on the received data to produce an output signal; and an exponential acceleration and deceleration circuit, operatively connected to receive the output signal from said linear acceleration and deceleration circuit, for effecting an exponential acceleration and deceleration computation on the output signal separately for each axis.

Claim 4

An acceleration/deceleration system for at least one of increasing a feed speed up to a command speed and reducing the feed speed in dependence upon feed speed and displacement signals, comprising: an interpolator, operatively connected to receive the feed speed and displacement signals, for computing and issuing interpolation data on a plurality of axes in dependence upon the feed signal and the displacement signal; a linear acceleration and deceleration circuit, operatively connected to receive the interpolation data issued from said interpolator on each axis per one sampling cycle, for effecting a linear acceleration and deceleration computation on the received data to produce an output signal; and an exponential acceleration and deceleration circuit, operatively connected to receive the output signal from said linear acceleration and deceleration circuit, for effecting an exponential acceleration and deceleration computation on the output signal separately for each axis.

Claim 5

An acceleration and deceleration system as recited in claim 1, wherein said linear acceleration and deceleration circuit comprises: a predetermined number of buffer registers, operatively connected to receive the input data, for producing a buffered signal; a first adder, operatively connected to the buffer registers and to receive the input data, for subtracting the buffered signal from the input data to produce a first calculated signal; an accumulator, operatively connected to said first adder, for storing the first calculated signal; a sum register, operatively connected to said accumulator and said first adder, for storing the first calculated signal and supplying the first calculated signal to said first adder, said first adder adding a previously generated first calculated signal to subsequently generated input data and buffer signals to produce a subsequent first calculated signal; and a divider, operatively connected to said accumulator, for dividing the first calculated signal by the predetermined number to produce a second calculated signal, and wherein said exponential acceleration and deceleration circuit comprises: a combination circuit, operatively connected to said divider, for subtracting the speed command signal from the second calculated signal to produce a combined signal; a combined signal register, operatively connected to said combination circuit, for storing the combined signal; a second adder operatively connected to said combined signal register for accumulating the combined signal in dependence upon pulses received at a fixed rate to produce a combined signal sum; and an accumulator, operatively connected to said second adder, for storing the combined signal sum and producing the speed command signal in dependence upon a carry generated by accumulating the combined signal, said accumulator having a number of bits equal to the predetermined number of said buffer registers.

Claim 6

An acceleration and deceleration system as recited in claim 2, wherein said linear acceleration and deceleration circuit comprises: a predetermined number of buffer registers, operatively connected to receive the input data, for producing a buffered signal; a first adder, operatively connected to the buffer registers and to receive the input data, for subtracting the buffered signal from the input data to produce a first calculated signal; an accumulator, operatively connected to said first adder, for storing the first calculated signal; a sum register, operatively connected to said accumulator and said first adder, for storing the first calculated signal and supplying the first calculated signal to said first adder, said first adder adding a previously generated first calculated signal to subsequently generated input data and buffer signals to produce a subsequent first calculated signal; and a divider, operatively connected to said accumulator, for dividing the first calculated signal by the predetermined number to produce a second calculated signal, and wherein said exponential acceleration and deceleration circuit comprises: a combination circuit, operatively connected to said divider, for subtracting the speed command signal from the second calculated signal to produce a combined signal; a combined signal register, operatively connected to said combination circuit, for storing the combined signal; a second adder operatively connected to said combined signal register for accumulating the combined signal in dependence upon pulses received at a fixed rate to produce a combined signal sum; and an accumulator, operatively connected to said second adder, for storing the combined signal sum and producing the speed command signal in dependence upon a carry generated by accumulating the combined signal, said accumulator having a number of bits equal to the predetermined number of said buffer registers.