PCM signal transmission system

Claim 3

A system for transmitting PCM signals according to claim 1 wherein said transmitting means comprises means for selecting the length of said level reversal interval to be shorter than the longest level change interval determined pursuant to the specified rule of modulation.

Claim 4

A system for transmitting PCM signals according to claim 1 wherein said transmitting means comprises means for selecting the length of said level reversal interval to be equal to the longest level change interval determined pursuant to the specified rule of modulation.

Claim 5

A system for transmitting PCM signals according to claim 1 wherein said transmitting means comprises means for providing said synchronizing interval for every sampling interval.

Claim 6

A system for transmitting PCM signals According to claim 1 wherein said transmitting means comprises means for selecting said level reversal interval to be the same length as the longest level change interval as determined pursuant to said specified rule of modulation.

Claim 7

A system for transmitting PCM signals according to claim 1 wherein said transmitting means comprises means for modulating said signals in accordance with a Bi-phase modulation method and said means for including comprises means for setting a first bit of said level reversal interval at a "0" level.

Claim 8

A system for transmitting PCM signals according to claim 6 wherein said transmitting means comprises means for maintaining signals in said synchronizing interval at a constant level over a plurality of bit times.

Claim 9

A system for transmitting PCM signals according to claim 1 wherein said transmitting means comprises means for modulating said signals in accordance with a PE modulation method and said means for including comprises means for setting 2 first bits of said level reversal interval to be "01" or "10".

Claim 10

A system for transmitting PCM signals according to claim 8 wherein said transmitting means comprises means for maintaining signals in said synchronizing interval at a constant level over a plurality of said bit times and said means for setting is operable for setting 2 first bits of said level reversal interval to "01" and "10" when that level is "HIGH" and "LOW", respectively.

Claim 11

A system for transmitting PCM signals according to claim 1 wherein said transmitting means comprises means for modulating said signals in accordance with any one of a MFM modulation method, a ZM modulation method, a M 2 FM modulation method, a 4/5 MNRZI method and a 3PM modulation method.

Claim 12

A system as recited in claim 1 wherein said means for transmitting includes modulating means for modulating said PCM signals according to said specified rule of modulation, and wherein said means for including comprises reversal means separate from said modulating means.

Claim 15

A system for transmitting PCM signals according to claim 12 wherein said means for providing comprises means for transmitting a non-modulated signal of a predetermined duration within said violating synchronizing interval.

Claim 16

A system for transmitting PCM signals according to claim 12 wherein said second means for generating comprises means for selecting for said second predetermined duration the longest permissible duration conforming to the specified rule of modulation.

Claim 17

A system for transmitting PCM signals according to claim 12 wherein said means for transmitting includes clocked bistable means receiving an input signal for controlling an output signal thereof by inverting or maintaining the outputting signal in accordance with a binary value of said input signal, said first means for generatng said synchronizing interval comprising gating means receiving as inputs a synchronizing gate signal, a transfer clock signal, a gate signal for setting forth a level reversal interval subsequent to said synchronizing interval, and a PCM signal to be transmitted, and providing an output signal for input to said means for transmitting.

Claim 18

A system for transmitting PCM signals according to claim 15 wherein said bistable means comprises JK flip-flop means receiving said output signal from said first means for generating and receiving a clock input signal having a frequency twice the frequency of said transfer clock signal, and wherein said first means for generating includes logic gate means for providing an output signal representing a logic AND of said synchronizing gate signal AND said transfer clock signal OR said signal to be transmitted AND said gate signal for setting forth said level reversal interval.

Claim 19

A system for transmitting PCM signals according to claim 12 wherein said system further comprises receiving means for receiving said modulated signal and for outputting a demodulated data signal, a transfer clock signal and sampling interval clock signals.

Claim 20

A system for transmitting PCM signals according to claim 17 wherein said receiving means includes tandem connected D-type flip-flop means providing outputs to exclusive OR gate means, said exclusive OR gate means providing an output to a further D-type flip-flop means outputting said demodulated data signal, said receiving means further including edge signal deriving means for providing edge signals for received data, one shot multivibrator means for providing on one output terminal said transfer clock signal and on an inverted output terminal a clock signal for said tandem connected D-type flip-flop means, said tranfer clock signal connected to said further D-type flip-flop means for providing a clock signal thereto; and retriggerable one shot multivibrator means receiving said edge signal and having a predetermined bit hold time for outputting said sampling interval clock signal.

Claim 21

A system as recited in claim 12 wherein said means for transmitting includes modulating means for modulating said PCM signals according to said specified rule of modulation, and wherein said second means comprises reversal means separate from said modulating means.

Claim 22

A system for transmitting PCM signal according to claim 12, wherein said second means is operable for generating said level reversal interval in a bit time immediately following each said synchronizing interval.