Static bistable flip-flop circuit obtained by utilizing CMOS technology

Claim 1

A static bistable flip-flop circuit, produced by CMOS technology, comprising an input, an output, a first inverter, a first switch connecting the input of the flip-flop to the input of the first inverter, a second inverter, a second switch connecting the output of the first inverter to the input of the second inverter, a third inverter, a third switch connecting the output of the third inverter to the input of the first inverter, a fourth inverter, a fourth switch connecting the output of the fourth inverter to the input of the second inverter; the output of the first inverter being connected to the input of the third inverter, the output of the second inverter being connected to the input of the fourth inverter; the first switch and the fourth switch being simultaneously controlled by a first clock signal and the second and the third switches being simultaneously controlled by a second clock signal in phase opposition with the first, wherein: each switch is constituted by a single field effect N channel transistor, the gate of first and fourth switches is controlled by the first clock signal and the gate of second and third switches is controlled by the second clock signal; and including two MOS P channel transistors, the first P channel transistor being placed in parallel with the third switch and having its gate connected to a first circuit connecting point so that it is conductive at least when the output of the first inverter is at a low logic level, and the second P channel transistor being placed in parallel with the fourth switch and having its gate connected to a second circuit connecting point so that it is conductive at least when the output of the second inverter is at a low logic level.