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JPS6079599A Expired / Lapsed JP ⏱️ 0.0 years remaining

Shift register circuit

Assignee: NEC Corp
•
Filing: 1983-10-05
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Granted: —
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Expires: 2003-10-05
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Abstract

Abstract PURPOSE:To reduce the number of inputs of clock signals to simplify the constitution by using only one N-channel IGFET and only one P-channel IGFET as IGFETs operated as transfer switches. CONSTITUTION:When a clock signal V (P4) is in the high level, an N-channel IGFETQ9 is made conductive, and a P-channel IGFETQ10 is made non-conductive, and an input signal I3 is transferred to a node 7 and is amplified by an inverting amplifier A6. At this time, voltages of a node 9 and an output terminal O3 are held in preceding voltages because the IGFETQ10 is made non-conductive. When the signal V (P4) is in the low level, the IGFETQ9 is made non-conductive, and a voltage V of nodes 7 and 8 is held in the preceding voltage, but the IGFETQ10 is made conductive, and the voltage V of the node 8 is transferred to the node 9, and an inverted signal of the node 9 is outputted to the output terminal O3.

Inventors

  • 👤 Eiji Sugimoto
  • 👤 栄治 杉本

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 14:09
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28

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