Static semiconductor memory device

Claim 2

A static semiconductor memory device, comprising: a memory cell matrix comprised of memory cells arranged in rows and columns; a row address decoder for selecting one of said rows; a set of address input terminals for receiving address signals; a sense amplifier for operatively amplifying data from one of said columns; a latching circuit for operatively holding data amplified by said sense amplifier; an internal control circuit for generating first to third control signals when at least one of said address singals is changed in level, said internal control circuit generating said first and second control signals when a level of said changed address signal is in the range of V 1 to V 2 , and generating said third control signal when a level of said changed address signal is in the range of V 3 to V 4 , respectively; means for applying said first control signal to said row address decoder, said row address decoder being enabled by said first control signal and determining the selection of a row based on said changed address signal when a level of said changed address signal is at V 5 ; means for applying said second control signal to said sense amplifier to thereby enable said sense amplifier; and means for applying said third control signal to said latching circuit to thereby leave said latching circuit in a precharging state; wherein the condition V 1 <V 3 <V 5 <V 4 <V 2 is satisfied.

Claim 3

A device according to claim 1, wherein said internal control circuit comprises: an address buffer for receiving the address signal, an address transition detecting circuit for generating an address transfer detection signal when said at least one address signal is changed in level; and an internal control signal generator for receiving the address transfer detection signal, and for generating said first to third control signals.

Claim 4

A device according to claim 2, wherein said address buffer comprises an inverter A connected to the address signal input, and wherein said address transition detecting circuit comprises inverters B and C connected in parallel with said inverter A, said three inverters A, B and C having drive element to load element conductance ratios rA, rB and rC set to satisfy the inequality rB<rA<rC, said inverter A generating a buffered address signal to be applied to said row address decoder, and outputs from said inverters B and C being used to generate said address transfer detection signal.

Claim 5

A static semiconductor memory device comprising; a memory cell matrix comprises of a plurality of memory cells arranged in rows and columns; a plurality of address input means for receiving address signals; a plurality of address buffers for generating true and complementary address signals from said address signals, each of said address buffers including a first inverter receiving one of said address signals; a plurality of address transfer detector circuits each generating an address transfer detection signal when one of said address signals is changed in level, and address transfer detection circuits each including a second inverter for receiving one of said address signals, a third inverter for receiving said one of said address signals and first logic circuit means responsive to outputs of said second and third inverters for generating said address transfer detection signal; said first to third inverters having drive element to load element conductance ratios rA, rB and rC such that rB<rA<rC, a row address decorder for selecting one of said rows; a sense amplifier for operatively amplifying data from one of columns; a latching circuit for operatively holding data amplified by said sense amplifier; and an internal control circuit for generating a first control signal for enabling said row address decoder, a second control signal for enabling said sense amplifier and a third control signal for leaving said latching circuit in a prechanging state, said internal control circuit including gate means receiving outputs of said address transfer detection circuit, a fourth inverter E receiving an output of said gate means, a fifth inverter F receiving said output of said gate means, first delay means responsive to an output of said fourth inverter for generating said first and second control signals and second delay means responsive to an output of said fifth inverter for generating said third control signal, said fourth and fifth inverters having drive element to load element conductance ratios rE and rF such that rE<rF.

Claim 6

A static semiconductor memory device comprising; a memory cell matrix comprises of a plurality of memory cells arranged in rows and columns; a plurality of address input means for receiving address signals; a plurality of address buffers for generating true and complementary address signals from said address signals, each of said address buffers including a first inverter receiving one of said address signals; a plurality of address transfer detector circuits each generating an address transfer detection signal when one of said address signals is changed in level, and address transfer detection circuits each including a second inverter for receiving one of said address signals, a third inverter for receiving said one of said address signals and first logic circuit means responsive to outputs of said second and third inverters for generating said address transfer detection signal; said first to third inverters having drive element to load element conductance ratios rA, rB and rC such that rB<rA<rC, a row address decorder for selecting one of said rows; a sense amplifier for operatively amplifying data from one of columns; a latching circuit for operatively holding data amplified by said sense amplifier; and an internal control circuit for generating a first control signal for enabling said row address decoder, a second control signal for enabling said sense amplifier and a third control signal for leaving said latching circuit in a prechanging state, said internal control circuit including gate means receiving outputs of said address transfer detection circuit, a fourth inverter E receiving an output of said gate means, a fifth inverter F receiving said output of said gate means, first delay means responsive to an output of said fourth inverter for generating said first and second control signals and second delay means responsive to an output of said fifth inverter for generating said third control signal, said fourth and fifth inverters having drive element to load element conductance ratios rE and rF such that rE<rF.