Method and a circuit arrangement for digital signal processing utilizing adaptive transversal filter techniques

Claim 3

The method of claim 1, and further comprising the steps of: iteratively forming the subsum signals by combining each successively-read subsum signal with a correction value to form a corrected new subsum signal and storing each new subsum signal in place of the corresponding read subsum signal.

Claim 4

The method of claim 2, and further comprising the steps of: during each iterative step, evaluating an output error signal with a control value; and correcting each read subsum signal with the evaluated output error signal.

Claim 5

The method of claim 3, wherein the step of evaluating is further defined as: evaluating the output error signal with the control value and with a sum of the squares of the tapped signal elements.

Claim 6

The method of claim 4, for a sign-symmetrical digital signal, wherein: the step of storing is further defined as storing subsum signals, which differ only with respect to their sign, only once; and the step of evaluating is further defined as adding and subtracting the successively read subsum signals in accordance with the actual combination of tapped signal elements to form the output signal and the new subsum signals.

Claim 7

The method of claim 1, wherein the step of storing is further defined as: storing only those subsum signals which differ from zero.

Claim 8

A circuit arrangement for digital signal processing with a settable adaptive transversal filter, comprising: an N-1 stage delay chain including an input for receiving a serial input digital signal having A possible values, and N/w group of, in each case, w consecutive taps for tapping signal elements; scanning means operating N/w times faster than said delay chain, including N/w groups of inputs respectively connected to a group of w consecutive taps, and an output; a coder including an input connected to said output of said scanning means for encoding scan signals, and an output; memory means including a write-read memory including a control input, a read output and a write output, said control input connected to said output of said coder, for storing subsum signals, said subsum signals corresponding to the N/w consecutive groups of A w possible combinations each of w consecutive tapped signal elements evaluated in accordance with the relative filter setting; and adder means comprising a first input circuit connected to said read output of said memory and to said output of said coder, a second input circuit and an output circuit connected to said second input circuit, said adder means operating in response to its input subsum signals during each delay step to provide a processed output signal.

Claim 9

A circuit arrangement for digital signal processing with a settable adaptive transversal filter, comprising: an N-1 stage delay chain including an input for receiving a serial input digital signal having A possible values, and N/w group of, in each case, w consecutive taps for tapping signal elements; scanning means operating N/w times faster than said delay chain, including N/w groups of inputs respectively connected to a group of w consecutive taps, and an output; a coder including an input connected to said output of said scanning means for encoding scan signals, and an output; memory means including a write-read memory including a control input, a read output and a write output, said control input connected to said output of said coder, for storing subsum signals, said subsum signals corresponding to the N/w consecutive groups of A w possible combinations each of w consecutive tapped signal elements evaluated in accordance with the relative filter setting; and adder means comprising a first input circuit connected to said read output of said memory and to said output of said coder, a second input circuit and an output circuit connected to said second input circuit, said adder means operating in response to its input subsum signals during each delay step to provide a processed output signal.

Claim 10

The circuit of claim 7, wherein said adder means constitutes a first adder means, and further comprising: second adder means comprising a first input circuit connected to said read output of said memory, a second input circuit for receiving an evaluated error signal, and an output connected to said write input of said write/read memory; and error evaluation means connected to said output of said coded and to said second input of said second adder means and operating to evaluate the error signal with a control value and to provide the evaluated error signal to said second adder means during each delay step.

Claim 11

The circuit arrangement of claim 8, wherein: said error evaluation means comprises means operating to evaluate an error signal with the control value and with a sum of the squares of the tapped signal elements.

Claim 12

The circuit arrangement of claim 9, wherein: said scanning means comprises a plurality of multiplexers each including N/w inputs respectively connected to corresponding ones of said taps of the individual groups of taps; and a synchronous clock generator connected to and synchronously clocking said multiplexers and said write/read memory.

Claim 13

The circuit arrangement of claim 7, wherein: said coder comprises a read only memory.

Claim 14

The circuit arrangement of claim 7 for processing ternary signals, and further comprising: input means for receiving and converting a ternary signal into a binary amount signal and a binary sign signal; and wherein said time delay chain comprises two identical tapped arms each receiving a respective binary signal; and said scanning means comprises a pair of scanning devices each connected between the taps of the respective arm and said coder.