Patent US4701860A successfully refreshed from Google Patents.
US4701860A
Expired / Lapsed
US
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Integrated circuit architecture formed of parametric macro-cells
Assignee: Harris Corp
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Filing: 1985-03-07
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Granted: 1987-10-20
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Expires: 2005-03-07
Abstract
Abstract An integrated circuit architecture methodology effectively comprises the use of high level building blocks (termed macro-cells) that are composed of a customized arrangement of a number of smaller but readily chip-layout repeatable building blocks termed micro-cells. The size of each macro-cell is determined by signal processing design/performance/operational parameters of the system. The internal configuration geometry and signal port connections of each microcell are customized for circuit packaging density, performance and interconnectability with other micro-cells.
Inventors
- 👤 James M. Mader
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:57
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1731; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F2111/00; G06F2111/20
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
270 words
A method of manufacturing an integrated circuit comprising the steps of: (a) storing a first library of a first plurality of different prescribed function-performing digital logic circuit devices of a first signal processing capacity capable of being implemented within said integrated circuit; (b) storing a second library of a second plurality of different prescribed function-performing digital signal processing devices of a second signal processing capacity greater than said first signal processing capacity and capable of being implemented within said integrated circuit by combinations of the digital logic circuit devices of said first library, prescribed characteristics of said second plurality of different prescribed function-performing digital signal processing devices being individually selectable, so that the signal processing function of a respective one of said second plurality of digital signal processing devices is established by a respective combination of plural ones of said first digital logic devices, thereby providing a respective signal processing device having said second signal processing capacity; (c) configuring said integrated circuit in the form of an interconnected arrangement of selected ones of the digital signal processing devices of said second library, prescribed characteristics of which are selected based upon signal processing parameters of said integrated circuit; (d) configuring said selected ones of the digital signal processing devices of said second library of respective combinations of selected ones of the digital logic circuit devices of said first library; and (e) forming an interconnected architecture of the selected ones of the digital signal processing devices of said second library as configured in step (d) in a body of semiconductor material, whereby a semiconductor chip architecture of said integrated circuit is realized.
Claim 2
Independent Claim
270 words
A method of manufacturing an integrated circuit comprising the steps of: (a) storing a first library of a first plurality of different prescribed function-performing digital logic circuit devices of a first signal processing capacity capable of being implemented within said integrated circuit; (b) storing a second library of a second plurality of different prescribed function-performing digital signal processing devices of a second signal processing capacity greater than said first signal processing capacity and capable of being implemented within said integrated circuit by combinations of the digital logic circuit devices of said first library, prescribed characteristics of said second plurality of different prescribed function-performing digital signal processing devices being individually selectable, so that the signal processing function of a respective one of said second plurality of digital signal processing devices is established by a respective combination of plural ones of said first digital logic devices, thereby providing a respective signal processing device having said second signal processing capacity; (c) configuring said integrated circuit in the form of an interconnected arrangement of selected ones of the digital signal processing devices of said second library, prescribed characteristics of which are selected based upon signal processing parameters of said integrated circuit; (d) configuring said selected ones of the digital signal processing devices of said second library of respective combinations of selected ones of the digital logic circuit devices of said first library; and (e) forming an interconnected architecture of the selected ones of the digital signal processing devices of said second library as configured in step (d) in a body of semiconductor material, whereby a semiconductor chip architecture of said integrated circuit is realized.
Claim 3
Dependent Claim
70 words
A method according to claim 1, wherein digital logic circuit devices of said first library have geometries and signal port configurations such that they may be physically arranged with one another on said chip to provide two dimensional alignment thereamong, thereby effectively compacting the geometry of a respective signal processing device of said second library resulting from the physical arrangement of the digital logic circuit devices of said first library.
Claim 4
Dependent Claim
63 words
A method according to claim 1, wherein digital logic circuit devices of a respective digital logic function as contained within said first library include a plurality of differently sized typed so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective signal processing device of said second library.
Claim 5
Dependent Claim
31 words
A method according to claim 1, wherein the signal processing devices of said second library include N-bit and N×M bit capacity digital signal processing devices, where N and M are integers.
Claim 6
Dependent Claim
53 words
A method according to claim 1, wherein the signal processing device of a second library include devices selected from a group consisting of a multi-bit register, a multi-bit comparator, a multi-bit ripple adder, a multi-bit random access memory, a multi-bit read only memory, a multi-word multiplier, a priority encoder and a multi-bit multiplexer.
Claim 7
Dependent Claim
30 words
A method according to claim 1, wherein said first signal processing capacity corresponds to single bit processing capacity, and said second signal processing capacity corresponds to a multi-bit processing capacity.
Claim 8
Dependent Claim
198 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library.
Claim 9
Dependent Claim
198 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library.
Claim 10
Dependent Claim
225 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library, and wherein the digital signal processing devices of said first library include N-bit and NXM bit capacity digital signal processing devices, where N and M are integers.
Claim 11
Dependent Claim
225 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library, and wherein the digital signal processing devices of said first library include N-bit and NXM bit capacity digital signal processing devices, where N and M are integers.
Claim 12
Dependent Claim
246 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library, and wherein the digital signal processing devices of said first library include devices selected from a group consisting of a multi-bit register, a multi-bit comparator, a multi-bit adder, a multi-bit random access memory, a multi-bit read only memory, a multi-word multiplier, a priority encoder and a multi-bit multiplexer.
Claim 13
Dependent Claim
246 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library, and wherein the digital signal processing devices of said first library include devices selected from a group consisting of a multi-bit register, a multi-bit comparator, a multi-bit adder, a multi-bit random access memory, a multi-bit read only memory, a multi-word multiplier, a priority encoder and a multi-bit multiplexer.
Claim 14
Dependent Claim
224 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library, and wherein said second signal processing capacity corresponds to a single bit processing capacity and said first signal processing capacity corresponds to a multi-bit processing capacity.
Claim 15
Dependent Claim
224 words
An integrated circuit comprising: a body of semiconductor material in which is arranged an interconnected architecture of a first plurality of respective prescribed digital signal processing devices of a first signal processing capacity selected from a first library containing a first plurality of different digital signal processing devices implementable within an integrated circuit by respective combinations of selected ones of a second library containing a second plurality of respective digital logic circuit devices of a second signal processing capacity smaller than said first signal processing capacity, the geometries and signal port configurations of the digital logic circuit devices of said second library being such that they may be physically arranged with one another in said semiconductor body to provide two dimensional alignment thereamong when combined to form respective ones of the digital signal processing devices of said first library, and wherein digital logic circuit devices of a respective digital logic function as contained within said second library include a plurality of differently sized types so as to enable geometrical alignment with respect to digital logic circuit devices that perform other digital logic functions when combined therewith to form a respective digital signal processing device of said first library, and wherein said second signal processing capacity corresponds to a single bit processing capacity and said first signal processing capacity corresponds to a multi-bit processing capacity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |