US4701841A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for altering data transmission modes
Assignee: Hewlett Packard Development Co LP
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Filing: 1984-07-25
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Granted: 1987-10-20
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Expires: 2004-07-25
Abstract
Abstract The present circuitry operates with a computer system which employs a CPU, memory, and other data handling devices such as peripherals and terminals. All of the foregoing elements of the computer system are connected to a major signal bus. The computer system functions by transmitting data and instructions from one element to another in accordance with a principal protocol. However, the present system does provide for decoding address signals, which are transmitted on the major signal bus, and if such address signals are acceptable to the memory then a new set of timing signals and a new set of protocol control signals are generated. In response to these new timing signals and new protocol control signals, data is transferred between the memory and the CPU at a faster rate and under a different protocol than the principal protocol thereby making the computer system function faster than heretofore.
Inventors
- 👤 Gerald O. Goodrich
- 👤 Michael M. Tehranian
- 👤 Donald A. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:43
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
167 words
A data transmission system comprising processor means for generating and outputting peripheral addresses and for exchanging data via a first data bus, said processor means further including first cont means for exchanging control signals via a second data bus; first peripheral system means, coupled to said processor means via said first data bus, for responding to a first one said peripheral addresses by exchanging said with said processor means along said first data bus at a first data rate; and second peripheral system means, coupled to said processor means via said first and second data buses, for responding to a second one of said peripheral addresses by exchanging said data with said processor means via said first data bus at a second data rate greater than said first data rate, said second peripheral system means further including second control means for exchanging signals with said processor means via said second data bus to permit said second peripheral means to exchange said data at said second data rate.
Claim 2
Dependent Claim
167 words
A data transmission system comprising processor means for generating and outputting peripheral addresses and for exchanging data via a first data bus, said processor means further including first cont means for exchanging control signals via a second data bus; first peripheral system means, coupled to said processor means via said first data bus, for responding to a first one said peripheral addresses by exchanging said with said processor means along said first data bus at a first data rate; and second peripheral system means, coupled to said processor means via said first and second data buses, for responding to a second one of said peripheral addresses by exchanging said data with said processor means via said first data bus at a second data rate greater than said first data rate, said second peripheral system means further including second control means for exchanging signals with said processor means via said second data bus to permit said second peripheral means to exchange said data at said second data rate.
Claim 3
Dependent Claim
110 words
The data transmission system of claim 1 further including timing means, coupled to said second data bus, for providing timing and control signals for exchanging data at said second data rate; wherein said second control means of said second peripheral system means includes decoding means, coupled to said first and second buses, for decoding said peripheral addresses and for producing a control signal on said second data bus in response to said second one of peripheral addresses; and wherein said first control means of said processing means includes means for generating a timing signal on said second data bus in response to said control signal to activate said timing means.
Claim 4
Dependent Claim
40 words
The data transmission system of claim 2 wherein said timing means includes means for generating a peripheral control signal in response to said timing signal to activate said second peripheral system means for exchanging data at said second data rate.
Claim 5
Dependent Claim
17 words
The data transmission system of claim 3 wherein said second peripheral system means includes a memory system.
Claim 6
Dependent Claim
30 words
The data transmission system of claim 4 wherein said memory includes two memory sections; and a multiplexer coupled to said two memory sections for selecting outputs from said memory sections.
Claim 7
Dependent Claim
61 words
The data transmission system of claim 5 wherein said first control means of said processor means is responsive to a bus request signal and includes signal delay circuitry for producing a delayed output signal delayed by a predetermined amount from said bus request signal; and logic circuitry for producing said timing signal from said delayed output signal and said control signal.
Claim 8
Dependent Claim
32 words
The data transmission system in claim 1 wherein said processor means includes a central processor unit and said second peripheral system means includes a memory system used by said central processor unit.
Claim 9
Dependent Claim
17 words
The data transmission system of claim 7 wherein said first peripheral system means includes an input/output device.
Claim 10
Dependent Claim
47 words
The data transmission system in claim 1 further including timing means, coupled to said second peripheral system means and to said processor means for providing timing and control signals for exchanging data between said second peripheral system means and said processor means at said second data rate.
Claim 11
Dependent Claim
33 words
The data transmission system of claim 1 wherein said second peripheral system means is located physically closer to said processing means along said first data bus than is said first peripheral system means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-19 | 1991-04-20 | 1991-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-19 | 1995-04-20 | 1995-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-19 | 1999-04-20 | 1999-10-20 | $7700.00 | Window Closed / Lapsed |