Selectively enabled image signal processing circuit using recursive filtering

Claim 1

An image signal processing circuit device comprising: a delay circuit for delaying an input signal by a time corresponding to one horizontal scanning period, a first level regulator for multiplying an output signal of said delay circuit by a factor K to regulate an amount of feedback, where K is smaller than unity, a first adder for summing said video signal and an output signal of said first level regulator, said first adder having an output connected to an input terminal of said delay circuit, a second level regulator for multiplying said output signal of said delay circuit by a factor (1-K), a first phase inverter for inverting a phase of an output signal of said second level regulator, a second adder for summing said video signal and an output signal of said first phase inverter, an amplitude limiter for limiting an amplitude of an output signal of said second adder, a third level regulator for regulating an output signal of said amplitude limiter to a noise level of said video signal, a second phase inverter for inverting a phase of an output of said third level regulator, and a third adder for summing said video signal and an output signal of said second phase inverter, said third level regulator, said second phase inverter, and said third adder constituting an operation circuit.