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US4700466A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing semiconductor device wherein silicon substrates are bonded together

Assignee: Toshiba Corp
•
Filing: 1986-02-03
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Granted: 1987-10-20
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Expires: 2006-02-03
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Abstract

Abstract A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other. The contacting substrates are then placed in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealed at a temperature of not less than 200° C. so as to bond them together, thereby forming the second impurity-doped layer consisting of the third impurity doped layer and the second silicon substrate.

Inventors

  • 👤 Akio Nakagawa
  • 👤 Hiromichi Ohashi
  • 👤 Tsuneo Ogura
  • 👤 Masaru Shimbo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:38
CPC Classifications
H; H10; H10P; H10P70/00; H10P70/10; H10P70/15; H10P10/00; H10P10/12; H10P10/128

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 195 words
A method of manufacturing a semiconductor device, wherein a silicon wafer having a first impurity-doped layer and a second impurity doped layer with a higher impurity concentration than said first impurity-doped layer is formed, comprising the steps of: providing a first silicon substrate having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of said first impurity-doped layer, said third impurity-doped layer having a mirror-polished surface; providing a second silicon substrate having a higher impurity concentration than that of said first impurity-doped layer and the same conductivity type as said third impurity-doped layer, said second silicon substrate having a mirror-polished surface; bringing the mirror polished surfaces of said third impurity-doped layer and said second silicon substrate into contact in a clean atmosphere so that virtually no foreign substances are present therebetween; and annealing said first and second silicon substrates with the mirror-polished surfaces in contact with each other at a temperature of at least 200° C. so as to bond said substrates together without fusion, thereby forming a silicon wafer with said third impurity-doped layer and said second substrate bonded together and forming a second impurity-doped layer.
Claim 2
Independent Claim 195 words
A method of manufacturing a semiconductor device, wherein a silicon wafer having a first impurity-doped layer and a second impurity doped layer with a higher impurity concentration than said first impurity-doped layer is formed, comprising the steps of: providing a first silicon substrate having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of said first impurity-doped layer, said third impurity-doped layer having a mirror-polished surface; providing a second silicon substrate having a higher impurity concentration than that of said first impurity-doped layer and the same conductivity type as said third impurity-doped layer, said second silicon substrate having a mirror-polished surface; bringing the mirror polished surfaces of said third impurity-doped layer and said second silicon substrate into contact in a clean atmosphere so that virtually no foreign substances are present therebetween; and annealing said first and second silicon substrates with the mirror-polished surfaces in contact with each other at a temperature of at least 200° C. so as to bond said substrates together without fusion, thereby forming a silicon wafer with said third impurity-doped layer and said second substrate bonded together and forming a second impurity-doped layer.
Claim 3
Dependent Claim 32 words
A method according to claim 1, wherein said first and second impurity-doped layers are of the same conductivity type, and said first semiconductor substrate consists of said first and third impurity-doped layers.
Claim 4
Dependent Claim 69 words
A method according to claim 1, wherein said first and second impurity-doped layers are of different conductivity types; and said first semiconductor substrate consists of said first impurity-doped layer, a fourth impurity-doped layer formed thereon which has a higher impurity concentration than that of said first impurity-doped layer and is of the same conductivity type as that of said first impurity-doped layer, and said third impurity-doped layer formed thereon.
Claim 5
Dependent Claim 22 words
A method according to claim 1, wherein said semiconductor device is a diode, and said second impurity-doped layer serves as a cathode.
Claim 6
Dependent Claim 28 words
A method according to claim 1, wherein said semiconductor device is a conductivity modulation type metal oxide semiconductor device, and said second impurity-doped layer serves as an emitter.
Claim 7
Dependent Claim 18 words
A method according to claim 1, wherein a roughness of the mirror-polished surface is not more than 500Å.
Claim 8
Dependent Claim 19 words
A method according to claim 1, wherein an annealing temperature falls within the range of 1,000° to 1,200° C.
Claim 9
Dependent Claim 29 words
A method according to claim 1, wherein an oxide film is formed on said third impurity-doped layer, comprising removing the oxide film from said third impurity-doped layer before bonding.
Claim 10
Dependent Claim 32 words
A method according to claim 1, wherein said first and second impurity-doped layers are of the same conductivity type, and said first semiconductor substrate consists of said first and third impurity-doped layers.
Claim 11
Dependent Claim 69 words
A method according to claim 1, wherein said first and second impurity-doped layers are of different conductivity types; and said first semiconductor substrate consists of said first impurity-doped layer, a fourth impurity-doped layer formed thereon which has a higher impurity concentration than that of said first impurity-doped layer and is of the same conductivity type as that of said first impurity-doped layer, and said third impurity-doped layer formed thereon.

References Cited (Backward Citations)

US2701326A Cited
US2743201A Cited
US3303549A Cited
US4613381A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-10-19 1991-04-20 1991-10-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-10-19 1995-04-20 1995-10-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-10-19 1999-04-20 1999-10-20 $7700.00 Window Closed / Lapsed

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